Abstract: A simulation system for use in testing a radar system comprises a coarse delay module, a fine delay module, and a doppler shift module. The coarse delay module is configured to receive a first stream of digital data samples that are sampled from a radar signal at a sample time period or a second stream of digital data samples that are processed by another simulation system component and delay the digital data samples by a selectable first delay time that is greater than or equal to the sample time period. The fine delay module is configured to receive the digital data samples and filter the digital data samples to represent delay by a selectable second delay time that is less than the sample time period. The doppler shift module is configured to receive the digital data samples and adjust a value of a frequency content of the fine delayed samples.

Abstract: A simulation system for use in testing a radar system comprises a coarse delay module, a fine delay module, and a doppler shift module. The coarse delay module is configured to receive a first stream of digital data samples that are sampled from a radar signal at a sample time period or a second stream of digital data samples that are processed by another simulation system component and delay the digital data samples by a selectable first delay time that is greater than or equal to the sample time period. The fine delay module is configured to receive the digital data samples and filter the digital data samples to represent delay by a selectable second delay time that is less than the sample time period. The doppler shift module is configured to receive the digital data samples and adjust a value of a frequency content of the fine delayed samples.

Abstract: A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.