Patents by Inventor Augusli Kifli
Augusli Kifli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8543950Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).Type: GrantFiled: June 7, 2012Date of Patent: September 24, 2013Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
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Publication number: 20120246604Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).Type: ApplicationFiled: June 7, 2012Publication date: September 27, 2012Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng (L. -T.) WANG, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horag Lin, Hsin-Po Wang
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Patent number: 7900107Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.Type: GrantFiled: August 20, 2008Date of Patent: March 1, 2011Assignee: Faraday Technology Corp.Inventors: Wang-Chin Chen, Augusli Kifli
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Publication number: 20100050030Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.Type: ApplicationFiled: August 20, 2008Publication date: February 25, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Wang-Chin Chen, Augusli Kifli
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Patent number: 7512851Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.Type: GrantFiled: July 29, 2004Date of Patent: March 31, 2009Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin (Sam) Wang, Ming-Tung Chang
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Patent number: 7331032Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).Type: GrantFiled: April 22, 2005Date of Patent: February 12, 2008Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L. -T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Xiaoqing Wen, Shih-Chia Kao, Shyh-Horng Lin, Hsin-Po Wang
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Patent number: 6957403Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).Type: GrantFiled: March 28, 2002Date of Patent: October 18, 2005Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-P Wang
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Publication number: 20050055617Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.Type: ApplicationFiled: July 29, 2004Publication date: March 10, 2005Inventors: Laung-Terng Wang, Khader Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin Wang, Ming-Tung Chang
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Publication number: 20040153926Abstract: A method and apparatus to test data and set/reset faults in a scan-based integrated circuit in a selected scan-test mode or self-test mode. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The method comprises shifting in a plurality of predetermined stimuli during scan-test or pseudo-random stimuli during self-test to the scan-based integrated circuit, using a set/reset enable (SR_EN) signal 383 and a scan enable (SE) signal 382 to capture faults to each scan cell, and shifting out the test responses for comparison or compaction. The apparatus or set/reset controller 375 further comprises using the set/reset enable (SR_EN) signal 383 and scan enable (SE) signal 382 to selectively propagate data faults or set/reset faults to the scan cells in the integrated circuit.Type: ApplicationFiled: October 24, 2003Publication date: August 5, 2004Inventors: Khader S. Abdel-Hafez, Laung-Terng Wang, Augusli Kifli, Fei-Sheng Hsu, Xiaoqing Wen, Meng-Chyi Lin, Hsin-Po Wang
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Publication number: 20030023941Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).Type: ApplicationFiled: March 28, 2002Publication date: January 30, 2003Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang