Patents by Inventor August Spannagel

August Spannagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual-level package
    Patent number: 8373996
    Abstract: Consistent with an aspect of the present disclosure, a package is provided that has a carrier and first and second substrates provided on the carrier. Conductive traces are provided on the first substrate (upper traces) and below it (lower traces) to provide two levels of electrical connectivity to a photonic integrated circuit (PIC) provided on the second substrate. As a result, an increased number of connections can be made to the PIC in a relatively small package, while maintaining adequate spacing and line widths for each trace. In addition, the lower traces are connected to bonding pads on the surface of the first substrate and are thus provided in the same plane as the upper traces. Testing of and access to both upper and lower traces is thus simplified.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: February 12, 2013
    Assignee: Infinera Corporation
    Inventors: Donald J. Pavinski, Jr., August Spannagel, Charles H. Joyner, Peter W. Evans, Matthew Fisher, Mark J. Missey
  • DUAL-LEVEL PACKAGE
    Publication number: 20110007486
    Abstract: Consistent with an aspect of the present disclosure, a package is provided that has a carrier and first and second substrates provided on the carrier. Conductive traces are provided on the first substrate (upper traces) and below it (lower traces) to provide two levels of electrical connectivity to a photonic integrated circuit (PIC) provided on the second substrate. As a result, an increased number of connections can be made to the PIC in a relatively small package, while maintaining adequate spacing and line widths for each trace. In addition, the lower traces are connected to bonding pads on the surface of the first substrate and are thus provided in the same plane as the upper traces. Testing of and access to both upper and lower traces is thus simplified.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 13, 2011
    Inventors: Donald J. Pavinski, August Spannagel, Charles H. Joyner, Peter W. Evans, Matthew Fisher, Mark J. Missey