Abstract: Described herein is a method for producing photochromic silicone hydrogel contact lenses in a relatively efficient and consistent manner from a polymerizable composition under a controlled thermal curing scheme. The main polymerizable components in the polymerizable composition are a high radical-reactive hydrophilic (meth)acrylamido monomer, a high radical-reactive siloxane-containing (meth)acrylamido monomer, and a polysiloxane vinylic crosslinker(s) free of low-reactive ethylenically unsaturated group as the main crosslinker. The thermal free radical initiator having a 10 hour half-life temperature (T10h?) of from about 50° C. to about 90° C. The controlled thermal curing scheme includes maintaining a first curing temperature of from about (T10h??20)° C. to about T10h?° C. for a first curing time and maintaining a second curing temperature of from about (T10h?+10)° C. to about (T10h?+35)° C. for a second curing time.

Abstract: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions.

Abstract: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions.

Abstract: A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.

Abstract: An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions.

Abstract: A logic circuit comprising a quaternary logic switching circuit which includes a multilevel storage cell (MLSC), and the trinary or variable threshold logic means to yield an improved space, power, and time-efficient performance device is disclosed. The present invention is used for the implementation of a customized new logic design to further improve the cost-effectiveness of the application. Advanced circuit solutions are provided using asynchronous clock controlled functional units which are field programmable. A diode capacitor ladder chain is also used on an on-chip power supply multiplier to support internal high voltage operations. A digital-to-analog-to-digital translation (DADT) apparatus is also provided utilizing the above identified circuits. Finally, a printed circuit board (PCB) net driver with a trinary signal wire provides 50% bandwidth increase over conventional binary solutions.

Abstract: A PCB subsystem of IC parts is proposed. The PCB assembly contains single or plural of chips, each contains Giga Byte storage and 10 k gate equivalent Schottky CMOS (SCMOS) based field programmable gate arrays (SFPGA). The process technology combines CMOS transistors, EEPROM transistors, and low barrier Schottky diodes. The circuit architecture mixes both hardwired and SFPGA functional units. System interface architecture is based on simple low speed host interface, medium speed local peripheral bus, and high-speed on-chip bus. 1.2V supply low power, high capacity, and high flexibility IC product applications are supported. Efficient system integrations prescribe chip implementations with a distributive computing power running with GHz, 100 MHz, and 10 MHz clock rates at various interfaces. Universal chip and OS supports high bandwidth data access, transport, and storage operations with re-configurable circuit units and special nets.

Abstract: A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.

Abstract: A 3 Dimensional EEPROM cell layout, process control, and device model means are proposed. This cell construct uses the pointing shapes of the intrinsic conducting electrodes, thin and high dielectric insulators to customize signal coupling capacitors between intrinsic terminals, and therefore to optimize cell efficiency and operating voltages. Array of the said cells are mixed with high density, low power Schottky-CMOS logic (SCL) gate arrays to implement various array operations. The invented memory-logic device possesses 4F2 area per storage unit with 4 multilevel charges, single contact space per logic fan-in or fan-out, and operates with 1.2V supply. We have disclosed our invention with means and control schemes to obtain a compact cell. This cell has properties based on 3D geometrical details including film edge shapes, and composition of insulating materials in the intrinsic electrode constructs.

Abstract: A FLASH memory has an array of FLASH cells that each store N multiple bits of information as charge stored on a floating gate. Reference voltages or currents are generated for each boundary between the 2N states or levels and for an upper limit and a lower limit reference for each state. A selected bit line driven by a selected FLASH cell generates a sense node that is compared to a full range of 3*2N-1 comparators in parallel. The compare results are decoded to determine which state is read from the selected FLASH cell. An in-range signal is activated when the sense node is between the upper and lower limit references. The target programming count or programming pulses is adjusted during calibration to sense in the middle of the upper and lower limit references. Margin between references is adjusted by calibration codes that select currents for summing.