Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

Abstract: A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

Abstract: A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: An integrated circuit device can include at least a first bi-directional biasing circuit having a first substrate portion containing a plurality of first transistors; a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code; a first detect circuit configured to generate a difference value between the first target values and a first limit value; and at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to first target values. Embodiments can also include a performance monitor section configured to determine a difference between the voltage of the first substrate portion and a target voltage. Control logic can generate first code values in response to the difference between the voltage of the first substrate portion and the target voltage. Methods are also disclosed.

Abstract: An integrated circuit can include an operational section comprising a first body bias circuit coupled to drive first body regions to a first bias voltage in response to at least first bias values; a second body bias circuit coupled to drive second body regions to a second bias voltage in response to at least second bias values; a plurality of monitoring sections formed in a same substrate as the operational section, each configured to output a monitor value reflecting a different process variation effect on circuit performance.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a current-to-voltage converter. The resistance of the current source is typically large enough so that noise from an op-amp included in the current-to-voltage converter is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the current-to-voltage converter, but not both, eliminating noise in the system produced by the current source.

Abstract: A hybrid circuit that decouples gains for a transmit signal and a receive signal of a broadband modem that is coupled to a telephone line is provided. The hybrid circuit includes a multi-port transformer, a pair of line matching resistors, and a bridge circuit. The multi-port transformer includes a line coil electrically coupled to a telephone line, a linedriver coil magnetically coupled to the line coil and a receive coil that is also magnetically coupled to the line coil. In an alternate embodiment, a hybrid circuit is provided that includes a multi-port transformer in which the line coil, linedriver coil and receive coil include two coil segments. A broadband modem incorporating a hybrid circuit of the present invention is also provided.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a current-to-voltage converter. The resistance of the current source is typically large enough so that noise from an op-amp included in the current-to-voltage converter is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the current-to-voltage converter, but not both, eliminating noise in the system produced by the current source.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a resistive transimpedance amplifier (TIA). The resistance of the current source is typically large enough so that noise from an op-amp included in the TIA is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the resistive transimpedance amplifier, but not both, eliminating noise in the system produced by the current source.

Abstract: A hybrid circuit that decouples gains for a transmit signal and a receive signal of a broadband modem that is coupled to a telephone line is provided. The hybrid circuit includes a multi-port transformer, a pair of line matching resistors, and a bridge circuit. The multi-port transformer includes a line coil electrically coupled to a telephone line, a linedriver coil magnetically coupled to the line coil and a receive coil that is also magnetically coupled to the line coil. In an alternate embodiment, a hybrid circuit is provided that includes a multi-port transformer in which the line coil, linedriver coil and receive coil include two coil segments. A broadband modem incorporating a hybrid circuit of the present invention is also provided.

Abstract: Certain aspects of a system for controlling power for a network interface controller device may comprise a precision voltage comparator that may instantaneously detect ramp up of a main voltage corresponding to a main voltage source in order to control the network interface controller device. A power monitor may detect when a threshold voltage of the main voltage is reached during the ramp up. A main voltage source switch and an auxiliary voltage source switch may switch an output from an auxiliary voltage to the main voltage source without the switches being simultaneously on. The power monitor may determine whether the main voltage is ramping up in excess of a determined rate and if so, may decrease a rate at which the main voltage ramps up. A current limiter and/or the power monitor may monitor and limit an inrush current caused during main voltage ramp up.