Abstract: In some embodiments, a DFE including: an input terminal configured to receive an input signal carrying a plurality of symbols; an adder circuit coupled to the input terminal of the DFE; a plurality of comparator circuits configured to receive respective threshold signals; a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, where: the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and the plurality of correction coefficients are independently adjusted based on a previously received symbol.

Abstract: The method and architecture improve the robustness of a synchronization system through a minimum latency loop, for Hard Disk Drives (HDD), for example, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first acquisition step of a known preamble signal pattern, for generating a timing periodic signal, followed by a second tracking step, for recovering phase, frequency and gain sampling errors of the synchronization signal including a header followed by an unknown data content. Advantageously, a feedback loop including a numeric preamble generator (NPG) is provided for obtaining a reduced latency in the acquisition phase. The NPG stores preamble values for different phase offset.

Abstract: A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.