Abstract: A receiver includes a memory, processing circuitry, and a memory protection unit. The processing circuitry is coupled to the memory, and has an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency. The processing circuitry includes one or more independently powered components adapted to write data to the memory. The memory protection unit is coupled to the memory, and monitors a power supply voltage level corresponding to each independently powered component and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.

Abstract: A receiver includes a memory, processing circuitry, and a memory protection unit. The processing circuitry is coupled to the memory, and has an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency. The processing circuitry includes one or more independently powered components adapted to write data to the memory. The memory protection unit is coupled to the memory, and monitors a power supply voltage level corresponding to each independently powered component and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.

Abstract: Image rejection factors are calibrated for a receiver circuit (106) during an initialization period. The image rejection factors are stored in a quasi non-volatile memory (124) associated with the receiver circuit (106). The quasi non-volatile memory (124) is powered from a first source (VDD A) during a first receiver mode and from a second source (VIO) during a second receiver mode.

Abstract: An apparatus comprises a circuit having a power supply node and a linear regulator configured to provide a regulated voltage at the power supply node of the circuit. The apparatus further comprises a switching regulator configured to provide input power to the linear regulator from a power source such as a battery. In some implementations, the circuit is a transceiver circuit.

Abstract: A metal mesh structure for use in an integrated circuit is described. In one embodiment, a semiconductor integrated circuit includes a first region including, for example, a device layer having one or more active semiconductor devices. The circuit also includes a second region, which may include a metalization layer including circuit wires. The circuit further includes a layer of metal mesh interposed between the first and second regions, and which may be implemented on at least a portion of another metalization layer.

Abstract: A technique includes generating an analog voltage to control a frequency for an oscillator. The analog signal is converted into a digital signal, and the frequency is controlled in response to the digital signal.

Abstract: A technique includes selectively coupling impedances to an oscillator to establish a first frequency of operation of the oscillator. The technique includes repeating the selective coupling in a feedback loop to cause the first frequency to be near a second frequency.

Abstract: An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terninal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.

Abstract: A voltage regulator configured to receive a supply voltage from a voltage supply and provide a regulated voltage to digital circuitry is provided. The voltage regulator comprises first circuitry configured to inhibit high frequency energy generated by the digital circuitry from transmitting into the voltage supply, second circuitry configured to inhibit low frequency energy generated by the digital circuitry from transmitting into the voltage supply, and third circuitry configured to maintain the regulated voltage at a substantially constant value in response to a current drawn by the digital circuitry.

Abstract: In one embodiment, the present invention includes a capacitor array that may provide a selected capacitance to a digitally controlled crystal oscillator (DCXO). The array may include multiple sections each having at least one array portion, where each section is to receive different significant portions of a digital control value. The different sections may have different coding schemes. Other embodiments are described and claimed.

Abstract: A semiconductor integrated circuit includes an inductor formed by a conductive loop that is fabricated on one or more metal layers. The inductor also includes a dielectric region provided adjacent to the conductive loop. The semiconductor integrated circuit may also include a pattern of electrically isolated metallic fill structures formed within the dielectric region.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: A controlled oscillator circuit includes an amplifier including a first transistor coupled between a first node and a reference node, and a second transistor coupled between a second node and the reference node. The gate of first transistor and the gate of the second transistor may be cross-coupled. The oscillator may also include one or more variable capacitance circuits coupled between the first node and the second node, each including a first capacitor coupled between the first node and a third node, and a second capacitor coupled between the second node and a fourth node. Each variable capacitance circuit may also include a third, a fourth and a fifth transistor interconnected to selectively couple the first and second capacitors to the reference node. The third, fourth and fifth transistors may be low voltage transistors and the first and the second transistors may be high voltage transistors.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.

Abstract: A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.

Abstract: A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.