Abstract: In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a0a1 . . . aN?1])=??i(?1)ai where the symbols ai belong to the set {0, 1} and the sum extends for values of i from 0 to N?1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS0+4.K, where K is an integer, RDS is the said running digital sum, RDS0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: The method and architecture improve the robustness of a synchronization system through a minimum latency loop, for Hard Disk Drives (HDD), for example, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first acquisition step of a known preamble signal pattern, for generating a timing periodic signal, followed by a second tracking step, for recovering phase, frequency and gain sampling errors of the synchronization signal including a header followed by an unknown data content. Advantageously, a feedback loop including a numeric preamble generator (NPG) is provided for obtaining a reduced latency in the acquisition phase. The NPG stores preamble values for different phase offset.

Abstract: A system for decoding digital signals subjected to block coding includes a post-processor that corrects the codewords affected by error, identifying them with the most likely sequence that is a channel sequence and that satisfies a syndrome check. The post-processor is a finite-state machine described by a graph that represents the set of error events. The post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths that accumulate an invalid number of error events or an excessive number of wrong bits, paths that accumulate a total reliability higher than a given threshold, paths with an invalid check on the received sequence, and paths that reveal an invalid syndrome after having reached a maximum number of events.

Abstract: A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

Abstract: In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a0a1 . . . aN−1])=−&Sgr;i(−1)ai where the symbols ai belong to the set {0,1} and the sum extends for values of i from 0 to N−1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS0+4.

Abstract: A method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system that combines a Soft Output Viterbi Algorithm SOVA, which has the capability of detecting the reliability of a discrete, equalized signal, and a post processor, which has the capability of detecting specific error events in said discrete, equalized signal, so as to correct error events and to generate an output bit stream.

Abstract: A system For decoding digital signals subjected to block coding comprising a post-processor which corrects the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor is a finite-state machine described by a graph which represents the set of error events, the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths which accumulate an invalid number of error events or an excessive number of wrong bits, paths which accumulate a total reliability higher than a given threshold, paths with a invalid check on the received sequence, and paths which reveal an invalid syndrome after having reached a maximum number of events.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.