Patents by Inventor Augustus K. Uht
Augustus K. Uht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8601245Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.Type: GrantFiled: July 15, 2011Date of Patent: December 3, 2013Assignee: Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Publication number: 20110276792Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.Type: ApplicationFiled: July 15, 2011Publication date: November 10, 2011Applicant: Board of Governors for Higher Education, State of Rhode Island an Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 7991980Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.Type: GrantFiled: October 20, 2008Date of Patent: August 2, 2011Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 7721048Abstract: A computer processing system is disclosed that includes a cache that includes cache blocks of data. The system includes a marking sub-system, an ordering sub-system, and a replacement sub-system. The marking sub-system identifies and marks cache blocks that were provided to the cache via a wrong path with marking data. The ordering sub-system provides an order in which the cache blocks of data will be replaced in the cache, and the ordering sub-system is responsive to the marking data. The replacement sub-system replaces cache blocks in the cache in accordance with the ordering sub-system as required.Type: GrantFiled: March 15, 2007Date of Patent: May 18, 2010Assignee: Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Resit Sendag, Ayse Yilmazer, Augustus K. Uht
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Patent number: 7555084Abstract: The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware.Type: GrantFiled: August 11, 2005Date of Patent: June 30, 2009Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventor: Augustus K. Uht
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Publication number: 20090043994Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.Type: ApplicationFiled: October 20, 2008Publication date: February 12, 2009Applicant: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 7409534Abstract: A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.Type: GrantFiled: August 31, 2006Date of Patent: August 5, 2008Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 7380108Abstract: A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.Type: GrantFiled: August 31, 2006Date of Patent: May 27, 2008Assignee: Board of Govenors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 7210025Abstract: A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.Type: GrantFiled: April 19, 2001Date of Patent: April 24, 2007Inventors: Augustus K. Uht, David Morano, David Kaeli
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Patent number: 6985547Abstract: The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware.Type: GrantFiled: November 26, 2003Date of Patent: January 10, 2006Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventor: Augustus K. Uht
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Patent number: 6976150Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.Type: GrantFiled: April 6, 2001Date of Patent: December 13, 2005Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantationsInventors: Augustus K. Uht, David Morano, David Kaeli
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Publication number: 20040174944Abstract: The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware.Type: ApplicationFiled: November 26, 2003Publication date: September 9, 2004Applicant: The Board of Governors for Higher Education, State of Rhode Island and Providence PlantatinsInventor: Augustus K. Uht
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Patent number: 5201057Abstract: An architecture for a central processing unit (cpu) provides for the extraction of low-level concurrency from sequential instruction streams. The cpu includes an instruction queue, a plurality of processing elements, a sink storage matrix for temporary storage of data elements, and relational matrixes storing dependencies between instructions in the queue. An execution matrix stores the dynamic execution state of the instructions in the queue. An executable independence calculator determines which instructions are eligible for execution and the location of source data elements. New techniques are disclosed for determining data independence of instructions, for branch prediction without state restoration or backtracking, and for the decoupling of instruction execution from memory updating.Type: GrantFiled: February 5, 1990Date of Patent: April 6, 1993Inventor: Augustus K. Uht