Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit that generates the third data record on the output side from the data records fed to the combination circuit on the input side to ascertain based on the third data record whether the first and second data records have been fed to the combination circuit on the input side. The combination circuit generates the datum of the third data record with the first data value, if the first and second data records were fed to the combination circuit on the input side.

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Abstract: An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Abstract: An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Abstract: A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.

Abstract: An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.

Abstract: An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Abstract: A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.

Abstract: A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Abstract: An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.