Abstract: The present description concerns a method for manufacturing a protection device against overvoltages, comprising the following successive steps: a) epitaxially forming, on a semiconductor substrate, a semiconductor layer; b) submitting the upper surface of the semiconductor layer to a fluorinated-plasma process; and c) forming an electrically-insulating layer over and contacting the upper surface of the semiconductor layer.

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.

Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.