Patents by Inventor Aurelien Nam Phong TRAN
Aurelien Nam Phong TRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095163Abstract: According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.Type: ApplicationFiled: September 8, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Shinichi KANNO, Aurelien Nam Phong TRAN, Yuki SASAKI
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Patent number: 11347479Abstract: A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.Type: GrantFiled: February 26, 2020Date of Patent: May 31, 2022Assignee: KIOXIA CORPORATIONInventors: Mel Stychen Sanchez Tan, Aurelien Nam Phong Tran, Ryuji Nishikubo, Norio Aoyama
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Publication number: 20210064345Abstract: A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.Type: ApplicationFiled: February 26, 2020Publication date: March 4, 2021Inventors: Mel Stychen Sanchez TAN, Aurelien Nam Phong TRAN, Ryuji NISHIKUBO, Norio AOYAMA
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Publication number: 20180267715Abstract: According to one embodiment, the memory system includes a nonvolatile memory including a plurality of blocks, and a controller circuit that controls execution of a data writing process and a garbage collection process. Each of the blocks is an unit of erasure. The data writing process includes a process of writing user data into the nonvolatile memory in accordance with a request from an external member. The garbage collection process includes a process of moving valid data in at least a first block into a second block among the blocks and invalidating the valid data in the first block to be erasable. Upon receiving a data write request from the external member, the controller circuit controls a length of a waiting time to be provided before or after the data writing process within a period from receiving the write request to returning a response to the external member.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Hiroki Matsudaira, Norio Aoyama, Ryoichi Kato, Taku Ooneda, Takashi Hirao, Aurelien Nam Phong Tran, Hiroyuki Yamaguchi, Takuya Suzuki, Hajime Yamazaki
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Patent number: 9304906Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.Type: GrantFiled: March 7, 2014Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Matsudaira, Takashi Hirao, Aurelien Nam Phong Tran
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Publication number: 20150074335Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki MATSUDAIRA, Takashi Hirao, Aurelien Nam Phong Tran
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Patent number: 8924636Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.Type: GrantFiled: September 11, 2012Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Hirao, Hirokuni Yano, Aurelien Nam Phong Tran, Mitsunori Tadokoro, Hiroki Matsudaira, Tatsuya Sumiyoshi, Yoshimi Niisato, Kenji Tanaka
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Publication number: 20130227246Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, an allowable value is set for the number of defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.Type: ApplicationFiled: September 11, 2012Publication date: August 29, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi HIRAO, Hirokuni YANO, Aurelien Nam Phong TRAN, Mitsunori TADOKORO, Hiroki MATSUDAIRA, Tatsuya SUMIYOSHI, Yoshimi NIISATO, Kenji TANAKA