Patents by Inventor Aurelien TAVERNIER

Aurelien TAVERNIER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006459
    Abstract: The present description concerns an optoelectronic device manufacturing method, comprising the following steps: forming, on the upper surface side of a first substrate (100), a plurality of LEDs (101), each formed of a three-dimensional semiconductor element; depositing, on the upper surface side of the first substrate, a first layer (205a) made of a first material different from silicon oxide, said first layer (205a) laterally surrounding and covering the LEDs (101) and having a planar upper surface; and depositing a second layer (205b) made of silicon oxide on the upper surface of the first layer (205a), wherein the first material is such that the first layer (205a) is selectively etchable over the LEDs (101) and that the second layer (205b) is selectively etchable over the first layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: January 4, 2024
    Applicant: Commissariat à l'Énergie Atomique etaux Énergies Alternatives
    Inventors: Aurelien Tavernier, Nicolas Posseme, Romain Sommer
  • Patent number: 9818621
    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Aurelien Tavernier, Qingjun Zhou, Tom Choi, Yungchen Lin, Ying Zhang, Olivier Joubert
  • Publication number: 20170243754
    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Aurelien TAVERNIER, Qingjun ZHOU, Tom CHOI, Yungchen LIN, Ying ZHANG, Olivier JOUBERT