Patents by Inventor Aurelio Giancarlo Mauri
Aurelio Giancarlo Mauri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240069749Abstract: A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.Type: ApplicationFiled: August 21, 2023Publication date: February 29, 2024Inventors: Augusto Benvenuti, Giovanni Maria Paolucci, Alessio Urbani, Gianpietro Carnevale, Aurelio Giancarlo Mauri
-
Publication number: 20230371264Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Albert Fayrushin, Kamal Karda, Gianpietro Carnevale, Aurelio Giancarlo Mauri
-
Patent number: 10796778Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: GrantFiled: November 25, 2019Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Publication number: 20200234781Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: ApplicationFiled: November 25, 2019Publication date: July 23, 2020Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Patent number: 10490292Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: GrantFiled: December 20, 2018Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Publication number: 20190147966Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: ApplicationFiled: December 20, 2018Publication date: May 16, 2019Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Patent number: 10170196Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: GrantFiled: December 20, 2017Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Patent number: 10170639Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: GrantFiled: January 4, 2016Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
-
Publication number: 20180114581Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Patent number: 9881686Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: GrantFiled: December 29, 2016Date of Patent: January 30, 2018Assignee: Micron Technology, Inc.Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Publication number: 20170110198Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Publication number: 20160133752Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: ApplicationFiled: January 4, 2016Publication date: May 12, 2016Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
-
Patent number: 9230986Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: GrantFiled: January 30, 2015Date of Patent: January 5, 2016Assignee: Micron Technology, Inc.Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
-
Patent number: 9190472Abstract: Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.Type: GrantFiled: June 2, 2014Date of Patent: November 17, 2015Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Aurelio Giancarlo Mauri, Akira Goda, Yijie Zhao
-
Publication number: 20150287472Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.Type: ApplicationFiled: June 22, 2015Publication date: October 8, 2015Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Patent number: 9064577Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body.Type: GrantFiled: December 6, 2012Date of Patent: June 23, 2015Assignee: Micron Technology, Inc.Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
-
Publication number: 20150140797Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
-
Patent number: 8946807Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: GrantFiled: January 24, 2013Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti
-
Publication number: 20140264447Abstract: Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.Type: ApplicationFiled: June 2, 2014Publication date: September 18, 2014Applicant: Micron Technology, Inc.Inventors: Paolo Tessariol, Aurelio Giancarlo Mauri, Akira Goda, Yijie Zhao
-
Publication number: 20140203344Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.Type: ApplicationFiled: January 24, 2013Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: John Hopkins, Darwin Franseda Fan, Fatma Arzum Simsek-Ege, James Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti