Abstract: A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Abstract: A method and system for transferring control information between a host and network processor is provided. The system includes, a snooping module that is coupled to a snooping memory bus; a network cache controller; a host process scheduler that communicates with the network cache controller; and a host cache controller that controls a host cache for transferring control information without polling. The method includes, invalidating a data block in a network cache, after a message is composed by the host processor; invalidating a status block in the network cache after the message is posted; and transferring control from the host processor to the network processor. The method also includes, invalidating a status segment in a network cache after data is transferred from a host cache to a network cache; and invalidating a status segment in the host cache after data has been injected to a network.

Abstract: A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.