Patents by Inventor Aurobindo Dasgupta

Aurobindo Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses, methods, and systems for enhanced matrix multiplier architecture
    Patent number: 11334647
    Abstract: Systems, methods, and apparatuses relating to enhanced matrix multiplier architecture are described.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Aurobindo Dasgupta, Sujal Vora
  • APPARATUSES, METHODS, AND SYSTEMS FOR ENHANCED MATRIX MULTIPLIER ARCHITECTURE
    Publication number: 20200410038
    Abstract: Systems, methods, and apparatuses relating to enhanced matrix multiplier architecture are described.
    Type: Application
    Filed: June 29, 2019
    Publication date: December 31, 2020
    Inventors: Aurobindo Dasgupta, Sujal Vora
  • Logic with state retentive sleep mode
    Patent number: 7649385
    Abstract: Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Aurobindo Dasgupta, Mark Schuelein
  • Logic with state retentive sleep mode
    Publication number: 20080030224
    Abstract: Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.
    Type: Application
    Filed: August 7, 2006
    Publication date: February 7, 2008
    Inventor: Aurobindo Dasgupta
  • Registers for an enhanced idle architectural state
    Publication number: 20070147572
    Abstract: Some embodiments of the invention include apparatus, systems, and methods to force values to output nodes of registers of at least one circuit unit of a device during an idle state to reduce leakage power in the circuit unit. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Aurobindo Dasgupta, Amit Bhalerao
  • Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold
    Patent number: 6480998
    Abstract: The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim net's neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: November 12, 2002
    Assignee: Motorola, Inc.
    Inventors: Pradipto Mukherjee, Aurobindo Dasgupta, David T. Blaauw, David R. Bearden