Abstract: An auxiliary BIST circuit is constructed in a primary chip to which a secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit. This allows direct test access to the secondary chip without the need for a separate BIST circuit to be included in the secondary IC chip and without using a primary BIST circuit of the primary IC chip to test the secondary chip.

Abstract: An improved testable semi-conductor device is disclosed. An auxiliary BIST circuit is constructed in a primary chip to which a secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit. This allows direct test access to the secondary chip without the need for a separate BIST circuit to be included in the secondary IC chip and without using a primary BIST circuit of the primary IC chip to test the secondary chip.

Abstract: A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available.

Abstract: A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.

Abstract: A sense amplifier latch voltage waveform generator circuit provides an output voltage waveform which first increases to a first potential level, which is just below the threshold voltage of a field effect transistor, and subsequently increases with an ever-increasing slope over a useful voltage range. The generated voltage waveform is applied to the gate terminal of a latch field effect transistor, which is part of a sense amplifier circuit that includes a cross-coupled pair of field effect transistors whose sources are coupled to the drain of the latch transistor and whose drain terminals receive differential memory signals. The generator circuit consists essentially of an input gating transistor, an output stage having serially connected pull-up and pull-down transistors, and another similar feedback stage which includes a bootstrap capacitor. The bootstrap capacitor is coupled to the output stage.

Abstract: A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

Abstract: A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.

Abstract: A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.