Patents by Inventor Austin C. Frenkel

Austin C. Frenkel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-silicide system in integrated circuit technology
    Patent number: 7843015
    Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: November 30, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
  • Conversion of transition metal to silicide through back end processing in integrated circuit technology
    Patent number: 7151020
    Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: December 19, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan, Darin A. Chan, Paul R. Besser, Paul L. King, Minh Van Ngo
  • Multi-silicide in integrated circuit technology
    Patent number: 6969678
    Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: November 29, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan