Patents by Inventor Austin Fowler

Austin Fowler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12287271
    Abstract: Methods and systems to assess clogging associated with a first well perform steps in order. A first well in maintained a quiescent state for a period of time. Water is not pumped from the first well in the quiescent state. A pump attached to the first well is turned to an ON state. Water is pumped from the first well during the ON state. A water sample is received from the first well during the ON state. The water sample is collected during a time period corresponding to a surge in mobile particles. A first concentration of mobile particles is determined during the surge. The first concentration of mobile particles is analyzed for clogging specific information related to a state of clogging associated with the first well.
    Type: Grant
    Filed: March 21, 2024
    Date of Patent: April 29, 2025
    Assignee: SEVEE & MAHER ENGINEERS, INC.
    Inventor: Bruce Austin Fowler
  • Patent number: 12270962
    Abstract: Methods and systems are used to estimate specific capacity of a first well where the steps are performed in order. At least two depth to water measurements are made along with a corresponding time of occurrence for each of the at least two depth to water measurements. The measurements occur during a start-up transient of the first well after the first well has been maintained in a quiescent state for a first period of time. An extrapolated depth to water is estimated at an extrapolated pumping time using a mathematical model. Inputs to the mathematical model are derived from the at least two depth to water measurements. A first specific capacity estimate is created for the first well using the extrapolated depth to water estimate and a fixed pumping rate.
    Type: Grant
    Filed: March 21, 2024
    Date of Patent: April 8, 2025
    Assignee: SEVEE & MAHER ENGINEERS, INC.
    Inventor: Bruce Austin Fowler
  • Publication number: 20250061370
    Abstract: Systems and methods for error detection in a quantum computing system are provided. In one example, the method includes obtaining a multidimensional quantum error detection graph. The multidimensional quantum error detection graph represents one or more quantum error detection measurements across a time period. The method includes determining a partitioning scheme and a fusing scheme for the multidimensional quantum error detection graph based at least in part on a decoding latency and a fusing latency. The method includes partitioning the multidimensional quantum error detection graph into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection graph based at least in part on the fusing scheme. The method includes operating a quantum computing system based at least in part on the decoded detection graph.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 20, 2025
    Inventors: Noah John Shutty, Austin Fowler
  • Publication number: 20240386306
    Abstract: The disclosure is directed to a method performed during an execution of a quantum algorithm, via a quantum computing system (QCS) that includes a set of qubits and a set of classical processor devices. The quantum algorithm includes a quantum error correction (QEC) code that includes a set of qubit measurements over the set of qubits. Prior to the execution of the QA, the classical processor devices generate a matching graph (MG). During the execution of the quantum algorithm, the following operations are interleaved. A current subset of qubit measurements is performed. The qubit measurements are based on the QEC code. The classical processor devices update the MG based on values of the current subset of qubit measurements. The set of classical processor devices decodes one or more qubit errors based on the updated MG.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventor: Austin Fowler
  • Publication number: 20240386307
    Abstract: The disclosure is directed to a method performed during an execution of a quantum algorithm, via a quantum computing system (QCS) that includes a set of qubits and a set of classical processor devices. The quantum algorithm includes a quantum error correction (QEC) code that includes a set of qubit measurements over the set of qubits. Prior to the execution of the QA, the classical processor devices generate a matching graph (MG). During the execution of the quantum algorithm, the following operations are interleaved. A current subset of qubit measurements is performed. The qubit measurements are based on the QEC code. The classical processor devices update the MG based on values of the current subset of qubit measurements. The set of classical processor devices decodes one or more qubit errors based on the updated MG.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventor: Austin Fowler
  • Patent number: 12104362
    Abstract: Methods and systems to assess clogging from bacteria associated with a first well are disclosed. The first well is maintained in a quiescent state for a first period of time. Water is not pumped from the first well in the quiescent state. A pump attached to the first well is turned to an ON state. Water is pumped from the first well during the ON state. A water sample is received from the first well during the ON state. The water sample is collected during a first time period corresponding to a surge in mobile particles. A first activity level for a first type of bacteria in the water sample is determined. The activity level is analyzed for clogging specific information related to a state of clogging associated with the first well.
    Type: Grant
    Filed: March 21, 2024
    Date of Patent: October 1, 2024
    Assignee: SEVEE & MAHER ENGINEERS, INC.
    Inventor: Bruce Austin Fowler
  • Patent number: 12026589
    Abstract: A computer-implemented method for correcting one or more errors in a quantum computing system can include obtaining, by a computing system comprising one or more computing devices, a plurality of weighted detection graphs, each of the plurality of weighted detection graphs being descriptive of a plurality of error detection measurements and having a plurality of weights, each of the weights respectively determined according to an error probability. The method can include generating, by the computing system, a plurality of reweighted detection graphs based at least in part on a correlation between physical errors in the quantum computing system. The method can include correcting, by the computing system, one or more errors in a quantum computing system based at least in part on a global decoding of the plurality of reweighted detection graphs.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: July 2, 2024
    Assignee: GOOGLE LLC
    Inventors: Austin Fowler, Alexandru Paler
  • Patent number: 11021937
    Abstract: Apparatuses and method to reduce a pore-water pressure of water within a subsurface formation below a first pressure, include creating a pressure discontinuity in a well for a first period of time. The pressure discontinuity is created using ambient ground water pressure. A ground water flow regulating device (GFRD) is used to create the pressure discontinuity such that the GFRD restricts ground water flow through the well, which causes a pressure below the GFRD to increase. A flow of ground water is released through the well casing after the first period of time under natural ground water pressure. The GFRD releases the flow of the ground water and the pore-water pressure decreases to a second pressure after the ground water is released and the second pressure is less than the first pressure, wherein a first purge cycle is accomplished.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 1, 2021
    Assignee: SEVEE & MAHER ENGINEERS, INC.
    Inventor: Bruce Austin Fowler
  • Patent number: 7966549
    Abstract: The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: June 21, 2011
    Assignee: Qucor Pty. Ltd.
    Inventors: Lloyd Hollenberg, Ashley Stephens, Andrew Greentree, Austin Fowler, Cameron Wellard
  • Publication number: 20080185576
    Abstract: This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.
    Type: Application
    Filed: March 1, 2007
    Publication date: August 7, 2008
    Inventors: Lloyd Hollenberg, Ashley Stephens, Andrew Greentree, Austin Fowler, Cameron Wellard