Abstract: Embodiments of systems and methods to determine all of the Functions that are associated with a multi-Function Peripheral Component Interconnect/Compute Express Link (PCIe/CXL) Field Replaceable Unit (FRU) for use in SPDM authentication of a PCIe/CXL FRU are disclosed. According to one embodiment, a multi-Function PCIe/CXL FRU includes multiple Functions that each are represented by a unique Device/Function path. A PCIe/CXL FRU includes computer-executable program instructions that cause it to receive a request from a Security Protocol and Data Model (SPDM) requester to obtain information about a plurality of Functions associated with the PCIe/CXL FRU, and respond to the request by sending a list of Device/Function paths to the SPDM requester. Each Device/Function path indicates the Function and the path to the Function associated with the PCIe/CXL FRU.

Abstract: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.

Abstract: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.

Abstract: An information handling system bus port above a subject information handling system bus device may host an information handling system bus out of band message access control list of information handling system bus target device identifiers of other information handling system bus connected devices that the subject device is permitted to communicate with. The port may compare an information handling system bus target device identification field in out of band messages from the subject device to the list and route only out of band messages from the subject device in which the target device identification in the target device identification field is on the access control list through the information handling system bus. The port may discard (and generate error notifications, statuses, etc.) for out of band messages in which the target device identification in the target device identification field is not on the access control list.

Abstract: An information handling system bus port above a subject information handling system bus device may host an information handling system bus out of band message access control list of information handling system bus target device identifiers of other information handling system bus connected devices that the subject device is permitted to communicate with. The port may compare an information handling system bus target device identification field in out of band messages from the subject device to the list and route only out of band messages from the subject device in which the target device identification in the target device identification field is on the access control list through the information handling system bus. The port may discard (and generate error notifications, statuses, etc.) for out of band messages in which the target device identification in the target device identification field is not on the access control list.

Abstract: An information handling system may include a processor, a basic input/output system (BIOS) configured to initialize the information handling system, and a management controller coupled to the processor and configured to provide out-of-band management of the information handling system. The BIOS may be configured to: subsequent to initialization of an operating system of the information handling system, receive a notification that an information handling resource has been hot-inserted into the information handling system; and delay processing of the information handling resource by the operating system until the management controller has performed a platform-specific configuration change to the information handling resource.

Abstract: An information handling system includes a processor, a peripheral component interconnect express (PCIe) endpoint, and a PCIe downstream port. The PCIe downstream port blocks PCIe vendor-defined messages (VDMs) from the PCIe endpoint as a default mode, changes to a second mode in response to the PCIe endpoint being verified, and allows PCIe VDMs from the PCIe endpoint while in the second mode.

Abstract: An information handling system may include a processor, a basic input/output system (BIOS) configured to initialize the information handling system, and a management controller coupled to the processor and configured to provide out-of-band management of the information handling system. The BIOS may be configured to: subsequent to initialization of an operating system of the information handling system, receive a notification that an information handling resource has been hot-inserted into the information handling system; and delay processing of the information handling resource by the operating system until the management controller has performed a platform-specific configuration change to the information handling resource.

Abstract: An information handling system reduces latency of input/output transactions. The information handling system includes a system memory and an accelerator. The accelerator intercepts a command response that is issued by the system memory, determines a correct drive from an incorrect drive based on an attribute of the command response, and maps an address of the command response and sends the command response to the correct drive. The no-response command is sent to the incorrect drive. The correct drive completes the command response, and the incorrect drive issues a response that is disregarded by the accelerator.

Abstract: An information handling system reduces latency of input/output transactions. The information handling system includes a system memory and an accelerator. The accelerator intercepts a command response that is issued by the system memory, determines a correct drive from an incorrect drive based on an attribute of the command response, and maps an address of the command response and sends the command response to the correct drive. The no-response command is sent to the incorrect drive. The correct drive completes the command response, and the incorrect drive issues a response that is disregarded by the accelerator.

Abstract: An information handling system includes a processor, a peripheral component interconnect express (PCIe) endpoint, and a PCIe downstream port. The PCIe downstream port blocks PCIe vendor-defined messages (VDMs) from the PCIe endpoint as a default mode, changes to a second mode in response to the PCIe endpoint being verified, and allows PCIe VDMs from the PCIe endpoint while in the second mode.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a port configured to couple a hot-pluggable device received in the information handling system to the processor. The port may comprise a hot-plug controller configured to detect the insertion of the hot-pluggable device into the information handling system and delay communication of a hot-plug interrupt to an operating system executing on the processor in response to the insertion of the hot-pluggable device in order to allow for platform-specific configuration of the hot-pluggable device.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a basic input/output system comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The basic input/output system may be further configured to, prior to boot of an operating system of the information handling system, initialize a virtual device controller emulating a hardware controller for controlling peripheral devices communicatively coupled to the processor, and cause the virtual device controller to interact with a driver executing on the operating system to control the peripheral devices.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a port configured to couple a hot-pluggable device received in the information handling system to the processor. The port may comprise a hot-plug controller configured to detect the insertion of the hot-pluggable device into the information handling system and delay communication of a hot-plug interrupt to an operating system executing on the processor in response to the insertion of the hot-pluggable device in order to allow for platform-specific configuration of the hot-pluggable device.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a basic input/output system comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The basic input/output system may be further configured to, prior to boot of an operating system of the information handling system, initialize a virtual device controller emulating a hardware controller for controlling peripheral devices communicatively coupled to the processor, and cause the virtual device controller to interact with a driver executing on the operating system to control the peripheral devices.

Abstract: A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device.

Abstract: Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU); a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU; a service processor operably coupled to the CPU and to the NVMe; and a memory operably coupled to the service processor, the memory including program instructions stored thereon that, upon execution by the service processor, cause the service processor to: receive performance data from the CPU, receive metrics data from a source other than the CPU, and control an amount of power provided to the NVMe device based, at least in part, upon the performance data and the metrics data.

Abstract: A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device.

Abstract: Systems and methods for managing power to Non-Volatile Memory Express (NVMe) devices. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU); a Non-Volatile Memory Express (NVMe) device operably coupled to the CPU; a service processor operably coupled to the CPU and to the NVMe; and a memory operably coupled to the service processor, the memory including program instructions stored thereon that, upon execution by the service processor, cause the service processor to: receive performance data from the CPU, receive metrics data from a source other than the CPU, and control an amount of power provided to the NVMe device based, at least in part, upon the performance data and the metrics data.

Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.