Patents by Inventor Avadh Patel

Avadh Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache memory architecture and policies for accelerating graph algorithms
    Patent number: 10417134
    Abstract: A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 17, 2019
    Assignee: Oracle International Corporation
    Inventors: Priyank Faldu, Jeffrey Diamond, Avadh Patel
  • CACHE MEMORY ARCHITECTURE AND POLICIES FOR ACCELERATING GRAPH ALGORITHMS
    Publication number: 20180129613
    Abstract: A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.
    Type: Application
    Filed: February 23, 2017
    Publication date: May 10, 2018
    Inventors: Priyank Faldu, Jeffrey Diamond, Avadh Patel
  • HARDWARE SUPPORT FOR DYNAMIC DATA TYPES AND OPERATORS
    Publication number: 20170315807
    Abstract: A decoder circuit may be configured to receive an instruction which includes a plurality of data bits and decode a first subset of the plurality of data bits. A transcode circuit may be configured to determine if the received instruction is to be modified and, in response to a determination that the received instruction is to be modified, modify a second subset of the plurality of data bits.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Jeffrey Diamond, Herbert Schwetman, Avadh Patel