Abstract: A gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.

Abstract: A circuit includes: an output terminal; a first transistor; and a clamp circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor coupled to the output terminal. The clamp circuit has a second transistor and a clamp controller. The second transistor has a first terminal, a second terminal, and a control terminal. The clamp controller has a first terminal, a second terminal, and a third terminal. The first terminal of the second transistor is coupled to the control terminal of the first transistor. The third terminal of the clamp controller is coupled to the control terminal of the second transistor. The clamp controller includes a capacitor having a first terminal and a second terminal. The first terminal of the capacitor is coupled to the third terminal of the clamp controller.

Abstract: Described embodiments include a voltage clamping circuit having a threshold-setting circuit with a threshold input and a threshold output. A switch has a first terminal coupled to the threshold input, a second switch terminal, and a switch control terminal. A first transistor is coupled between the threshold output and the switch control terminal, and has a first control terminal. A second transistor is coupled between the first control terminal and ground, and has a second control terminal. A first driver circuit has a first driver input and a first driver output. A second driver circuit has a second driver input coupled to the first driver input, and a second driver output. A third transistor is coupled between the threshold input and ground, and has a third control terminal that is coupled to the second control terminal and the second switch terminal.

Abstract: Described embodiments include a gate drive circuit with a first transistor coupled between an input voltage terminal and a switching terminal, and having a first control terminal. A second transistor is coupled between the switching terminal and ground, and has a second control terminal. A first driver circuit has a first driver output coupled to the first control terminal, a first positive supply input coupled to a bootstrap voltage terminal, and a first negative supply input coupled to the switching terminal. A second driver circuit has a second driver output coupled to the second control terminal, a second positive supply input coupled to a driver supply, and a first negative supply input coupled to ground. An active clamp circuit is coupled between the driver supply and ground, and prevents a voltage between the driver supply and ground from exceeding a threshold voltage.

Abstract: The techniques and circuits, described herein, include solutions for latch-up prevention in multi-phase direct current (DC) to DC converters by ensuring safe pulse width modulation (PWM) control sequencing. In some aspects a latch-up pre-detection circuit has first and second detection inputs configured to receive high-side and low-side PWM signals respectively. The latch-up pre-detection circuit is configured to monitor for a transition from a first state to a second state based on the first and second detection inputs. The transition from the first state to the second state may be associated with condition(s) favorable for latch-up. Upon detecting the transition from the first state to the second state, the latch-up pre-detection circuit can output a pulse signal to temporarily override the unsafe PWM control sequence and reduce the possibility of latch-up.

Abstract: A gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.

Abstract: A dual loop clamp circuit includes a clamp circuit and a low-side driver circuit. The clamp circuit includes a clamp enable output and a low-side clamp output. The low-side driver circuit includes a low-side control signal input and an output stage. The output stage includes a low-side drive output and an input. The low-side drive output is coupled to the low-side clamp output. The input of the output stage is coupled to the clamp enable output and the low-side control signal input.

Abstract: An adaptive clamp circuit includes a clamp circuit and a clamp control circuit. The clamp circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a switching terminal. The second current terminal is coupled to a ground terminal. The second transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the second transistor is coupled to the control terminal of the first transistor. The second current terminal of the second transistor is coupled to the switching terminal. The variable resistor is coupled between the control terminal of the second transistor and the ground terminal. The clamp control circuit is coupled between the switching terminal and the variable resistor.