Patents by Inventor Avani F. Trivedi

Avani F. Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950313
    Abstract: Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Avani F. Trivedi, Tracy D. Evans, Carla L. Christensen, Tomoko Ogura Iwasaki, Aparna U. Limaye
  • Publication number: 20210065820
    Abstract: Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Avani F. Trivedi, Tracy D. Evans, Carla L. Christensen, Tomoko Ogura Iwasaki, Aparna U. Limaye
  • Publication number: 20210064265
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.
    Type: Application
    Filed: August 17, 2020
    Publication date: March 4, 2021
    Inventors: Jianmin Huang, Aparna U. Limaye, Avani F. Trivedi, Tomoko Ogura Iwasaki, Tracy D. Evans
  • Publication number: 20210056019
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Aparna U. Limaye, Tracy D. Evans, Tomoko Ogura Iwasaki, Avani F. Trivedi, Jianmin Huang
  • Publication number: 20210057018
    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Tracy D. Evans, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang
  • Publication number: 20210055990
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Avani F. Trivedi, Jianmin Huang, Aparna U. Limaye, Tracy D. Evans
  • Publication number: 20210055878
    Abstract: Systems, apparatuses, and methods related to data compaction in memory or storage systems or sub-systems, such as solid state drives, are described. For example, one or more memory pages storing valid data can be identified from a first data block in a plane of a memory component and copied to a page buffer corresponding to the plane. A controller of the system or sub-system can determine whether the plane of the memory component has another data block with capacity to store the one or more memory pages and can copy the one or more memory pages from the page buffer either to the other data block or to a different data block in a different plane of the memory component.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang, Tracy D. Evans
  • Patent number: 10891063
    Abstract: Methods of operating an electronic system include allocating a group of memory cells of a plurality of groups of memory cells having a particular rank of a plurality of ranks for storing data of a particular data level of a plurality of data levels, determining a need for an additional group of memory cells for storing data of the particular data level, moving or discarding data from a different group of memory cells storing data of a different data level of the plurality of data levels in response to determining the need for the additional group of memory cells for storing data of the particular data level, and allocating the different group of memory cells for storing data of the particular data level.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Carla L. Christensen, Avani F. Trivedi, Tracy D. Evans
  • Publication number: 20200167087
    Abstract: Methods of operating an electronic system include allocating a group of memory cells of a plurality of groups of memory cells having a particular rank of a plurality of ranks for storing data of a particular data level of a plurality of data levels, determining a need for an additional group of memory cells for storing data of the particular data level, moving or discarding data from a different group of memory cells storing data of a different data level of the plurality of data levels in response to determining the need for the additional group of memory cells for storing data of the particular data level, and allocating the different group of memory cells for storing data of the particular data level.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Carla L. Christensen, Avani F. Trivedi, Tracy D. Evans