Abstract: In one embodiment, a method by an Energy processing Unit (EPU) of a computing system includes detecting an event that triggers an integrity verification on a block of the local memory, determining that a hash for the block of the local memory is available, causing data corresponding to the block of the local memory to be read from a source location in response to the determination, performing an in-line hash operation on the data corresponding to the block of the local memory, and comparing an output of the in-line hash operation and a known hash for the block of the local memory.

Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: A method for secure key exchange. The method comprises receiving a request to certify a key from a communication partner at an interface between an access and tamper resistant circuit block and exposed circuitry. Within the access and tamper resistant circuit block, a first random private key is generated. A corresponding public key of the first random private key is derived, and a cryptographic digest of the public key and attributes associated with the first random private key is generated. The generated cryptographic digest is signed using a second random private key that has been designated for signing by one or more associated attributes. The public key and the signature are then sent to the communication partner via the interface.

Abstract: A method for initializing components of an electronic device includes receiving an input signal at an initialization block; after receiving the input signal, changing a state of a finite state machine (FSM) of the initialization block; sending an initialization signal from the initialization block to a component on a chip; after sending the initialization signal, changing the state of the FSM; receiving a return signal from the component with the initialization block; and after receiving the return signal, changing the state of the FSM.

Abstract: Systems and methods for using a common fuse controller hardware design for different applications are described. A method includes specifying a first fuse map for a first system on a chip (SoC) and a second fuse map for a second SoC. The method further includes processing the first fuse map to generate a first hardware description language (HDL) file and processing the second fuse map to generate a second HDL file. The method further includes using a processor, compiling a common hardware state machine HDL file with the first HDL file to generate a first output file capturing behavior expressed in the first fuse map or compiling the common hardware state machine HDL file with the second HDL file to generate a second output file capturing behavior expressed in the second fuse map.

Abstract: A method for initializing components of an electronic device includes receiving an input signal at an initialization block; after receiving the input signal, changing a state of a finite state machine (FSM) of the initialization block; sending an initialization signal from the initialization block to a component on a chip; after sending the initialization signal, changing the state of the FSM; receiving a return signal from the component with the initialization block; and after receiving the return signal, changing the state of the FSM.

Abstract: Systems, circuits, and methods for clock domain crossing for an interface between logic circuits are provided. A circuit is configured to allow an exchange of signals between a first logic circuit clocked using a first clock signal having a first frequency and a second logic circuit clocked using a second clock signal having a second frequency different from the first frequency. The circuit includes a first circuit segment configured to receive a first control signal to select the second logic circuit and a second control signal to indicate an initiation of an access operation, and ensure that the second control signal maintains a relationship with the first control signal based on the second clock signal. The circuit further includes a second circuit segment configured to receive, from the second logic circuit, a third control signal indicating a readiness of the second logic circuit to complete the access operation.

Abstract: A system includes operational circuit blocks associated with configurable counter circuits. A configurable counter circuit is configured to control event signal when counting expires and includes a mode input configured to receive a setting of a programmable control event asynchronous mode and a programmable control event synchronous mode. Depending on the programmed mode and whether a control event has occurred in a previous synchronization period, the configurable counter circuit processes an associated operation responsive to issuance of a synchronization instruction or to issuance of a subsequent control event.

Abstract: A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.

Abstract: A system includes operational circuit blocks associated with configurable counter circuits. A configurable counter circuit is configured to control event signal when counting expires and includes a mode input configured to receive a setting of a programmable control event asynchronous mode and a programmable control event synchronous mode. Depending on the programmed mode and whether a control event has occurred in a previous synchronization period, the configurable counter circuit processes an associated operation responsive to issuance of a synchronization instruction or to issuance of a subsequent control event.

Abstract: An electronic device includes a configurable pulse generator configured to generate a programmable master pulse train. One or more functional circuits of the electronic device includes a programming interface to receive one or more a programmable slave pulse parameters for the one or more functional circuits. The programmable slave pulse parameters are dependent upon the programmable master pulse train. A slave pulse generator generates a slave pulse for one of the functional circuits based on the one or more programmable slave pulse parameters corresponding to the functional circuits relative to the programmable master pulse train.

Abstract: A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.