Abstract: Methods, apparatus and computer software products implement embodiments of the present invention that include receiving requests from clients to access a corpus of data that is replicated on a group of servers, and distributing the requests among the servers for execution in accordance with an allocation function, which indicates a respective fraction of the requests that is to be assigned to each of the servers for execution. Respective cache miss rates incurred by the servers in responding to the requests that are distributed to each of the servers are measured, and the allocation function is adjusted responsively to the cache miss rates.

Abstract: A method and system for collecting statistics associated with multiple memory nodes to determine if a read-only page is read accessed in aggregate by multiple processing devices of the multiple memory nodes at or above a first threshold value. If so, the read-only page may be replicated to an additional memory node. If a determination is made that the read-only page is read accessed in aggregate by the multiple processing devices below the first threshold value, the read-only page may be de-replicated upon receipt of a write request associated with the read-only page.

Abstract: Methods, apparatus and computer software products implement embodiments of the present invention that include receiving requests from clients to access a corpus of data that is replicated on a group of servers, and distributing the requests among the servers for execution in accordance with an allocation function, which indicates a respective fraction of the requests that is to be assigned to each of the servers for execution. Respective cache miss rates incurred by the servers in responding to the requests that are distributed to each of the servers are measured, and the allocation function is adjusted responsively to the cache miss rates.

Abstract: A method and system for managing message-signaled interrupt-based events sent from an event source to a host or a guest is disclosed. A central processing unit instructs an event source to write a message-signaled interrupt to a designated address of a random access memory of the host. The host or a guest of the central processing unit executes a memory monitoring instruction to the designated address. The host or the guest enters a wait state. The host or the guest detects a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. The host or the guest exits from the wait state. The host or the guest performs an atomic operation with respect to the event based on the data items in the message-signaled interrupt.

Abstract: Methods and systems for executing a request between a virtual machine and a paravirtualized machine are provided. The request is received from the virtual machine at a first shared memory of a hypervisor. The first shared memory is accessible to the virtual machine but not the paravirtualized machine. The request is transferred by the hypervisor from the first shared memory to a second shared memory of the hypervisor. The second shared memory is accessible to the paravirtualized machine but not the virtual machine. The request is intended for execution by the paravirtualized machine.

Abstract: A method and system for collecting statistics associated with multiple memory nodes to determine if a read-only page is read accessed in aggregate by multiple processing devices of the multiple memory nodes at or above a first threshold value. If so, the read-only page may be replicated to an additional memory node. If a determination is made that the read-only page is read accessed in aggregate by the multiple processing devices below the first threshold value, the read-only page may be de-replicated upon receipt of a write request associated with the read-only page.

Abstract: A method and system for permitting a guest to program a message-signaled interrupt-based device is disclosed. A hypervisor of a host detects a request by a guest to map an address range of memory of the guest to a message signaled-interrupt capability table associated with a device. The hypervisor maps the message signaled-interrupt capability table from a message signaled-interrupt capability register of a programmable interrupt controller associated with the host to the address range of memory of the guest. The hypervisor detects an attempt by the guest to program the device with the message-signaled interrupt configuration located in the address range of memory of the guest. The hypervisor programs the device with the message-signaled interrupt configuration specified by the guest in the address range of memory of the guest.

Abstract: A method and system for dynamically managing memory in a computing environment using a control monitor. The control monitor (e.g., a virtual machine monitor or operating system kernel) includes a nomination module configured to collect memory statistics associated with at least one memory node. Based on the memory statistics, the control monitor detects one or more first pages accessed from a remote memory node at or above an access threshold. The nomination module nominates, via a communication to at least one of a scheduler module and a memory manager of the control monitor, the one or more first pages for migration to the remote memory node.

Abstract: Methods and systems for managing requests for access to devices managed by a hypervisor in virtualized computing environment. A hypervisor receives a request for access to a device from a guest. The hypervisor provides an address hint associated with the device to the guest and an association between the address hint and the device is stored in a reference table. Upon receipt of a subsequent request from the guest including the address hint, the hypervisor performs a look-up in the reference table based on the address hint to identify the device and establishes access to the device by the guest.

Abstract: A method and system for managing a virtual computing system including an event source configured to send an event to a destination virtual machine (VM) executing a memory monitoring instruction on a designated address range of a host memory. A hypervisor instructs a destination virtual central processing unit (VCPU) associated with the destination VM to execute the memory monitoring instruction to the designated address range of a memory. A physical CPU associated with the designated address range is configured not to perform an exit to the hypervisor in response to execution of the memory monitoring instruction by the destination VCPU. The hypervisor instructs an event source to write data to the designated address range to send an event for performance by the destination VM, wherein the destination VM wakes up and performs the identified event in response to the event source writing to the identified address range.

Abstract: A method and system for managing a virtual computing system including a hypervisor managing a virtual machine (VM) configured to communicate with a thread executable by multiple host central processing units (CPUs), using memory monitoring instructions. The hypervisor provides the virtual machine with a first notification identifying a first designated memory range writeable by a virtual central processing unit (VCPU) associated with the virtual machine and a first instruction to write to the first designated memory range to communicate with the thread running on a first host CPU. The hypervisor further identifies movement of the thread from the first host CPU to a second host CPU and provides to the virtual machine a second notification identifying a second designated memory range and a second instruction to write to the second designated memory range to communicate with the thread running on the second host CPU.

Abstract: A virtual machine disk page detector running on a computing device detects guest disk cache usage. The detector detects a request from a virtual operating system to read an object into a virtual memory page from a virtual disk, maintains a record of a page identifier and a corresponding virtual disk address in a guest cache data structure, and modifies a protection identifier of the virtual memory page to indicate that the virtual memory page is protected.

Abstract: A mechanism for on-demand hypervisor memory mapping is disclosed. A method of the invention includes trapping an access instruction to a memory location from a virtual machine (VM) managed by a hypervisor of a host machine, determining whether a number of accesses to the memory location by the VM exceeds a threshold, if the number of accesses to the memory location by the VM does not exceed the threshold, then emulating the access instruction to the memory location on behalf of the VM, and if the number of accesses to the memory location by the VM exceeds the threshold, then allocating guest physical memory for the VM associated with the memory location.

Abstract: A method and system for managing a virtual computing system including a virtual machine (VM) configured to send an event to a host CPU executing a memory monitoring instruction. The virtual machine is configured to receive from a hypervisor a notification identifying an address range writeable by a virtual central processing unit (VCPU) associated with the virtual machine to send an event to a host central processing unit (CPU). The virtual machine is further configured to receive an instruction to write to the identified address range for sending an event to the host CPU. The VCPU of the virtual machine may then write data identifying an event for execution by the host CPU to the identified address range, without causing an exit to the hypervisor.

Abstract: Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.

Abstract: A computing apparatus identifies that a first processor of a host has forwarded information for a device to a second processor that controls the device. After identifying that the first processor has forwarded the information to the second processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus causes future information for the device to be forwarded to the second processor.

Abstract: A mechanism for memory change tracking during migration of a virtual machine (VM) with VM-controlled assigned peripherals is disclosed. A method of the invention includes informing a write tracking module of an interest by a hypervisor of a host machine in a specific memory location associated with a peripheral device that is controlled by a VM managed by the hypervisor, receiving notification from the write tracking module that the identified specific memory location has been modified by the peripheral device, and marking a memory page of the specific identified memory location as dirty in order for the migration of the memory page to be repeated as part of a migration process of the VM to a destination host machine.

Abstract: A system and methods for sending data from one process to another process (i.e., interprocess communication) are disclosed. In accordance with one embodiment, an operating system recognizes a request by a sending process to perform an asynchronous write to a pipe, and a request by a receiving process to perform an asynchronous read from the pipe, occurring in either order. The operating system then selects one of a plurality of mechanisms for providing the data to the receiving process.

Abstract: A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus identifies a device that is controlled by the virtual processor, wherein device interrupts for the device are forwarded to the virtual processor. The computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send the device interrupts to the second physical processor of the host, wherein the second physical processor of the host forwards the device interrupts to the virtual processor running on the second physical processor without generating an inter-processor interrupt.

Abstract: A computing apparatus identifies that a first processor of a host has forwarded information for a device to a second processor that controls the device. After identifying that the first processor has forwarded the information to the second processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus causes future information for the device to be forwarded to the second processor.