Abstract: An improved MOS E.sup.2 cell is described which includes a floating gate and a thin oxide region. Charge injected into the substrate is used to program the floating gate by hot electron injection through the tunnel oxide region. Erasing is accomplished by tunneling through the thin oxide region. With this arrangement, the capacitance coupling between the floating gate and control gate is greatly reduced, allowing the cell to be substantially smaller. Several novel inhibit modes permit the fabrication of an array without using a selection device for each of the cells.