Patents by Inventor Avi Mendelson
Avi Mendelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140049550Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.Type: ApplicationFiled: September 4, 2013Publication date: February 20, 2014Inventors: Hu Chen, Gao Ying, Zhou Xiaocheng, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
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Patent number: 8531471Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.Type: GrantFiled: December 30, 2008Date of Patent: September 10, 2013Assignee: Intel CorporationInventors: Hu Chen, Ying Gao, Zhou Xiaocheng, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
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Publication number: 20130187936Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.Type: ApplicationFiled: March 11, 2013Publication date: July 25, 2013Inventors: Zhou Xiaocheng, Shoumeng Yan, Gao Ying, Hu Chen, Peinan Zhang, Mohan Rajagopalan, Avi Mendelson, Bratin Saha
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Publication number: 20130132636Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: November 30, 2012Publication date: May 23, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20130132683Abstract: A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: December 13, 2012Publication date: May 23, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20130132622Abstract: A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: December 13, 2012Publication date: May 23, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20130111086Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: November 30, 2012Publication date: May 2, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20130097353Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: December 6, 2012Publication date: April 18, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20130091317Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: November 30, 2012Publication date: April 11, 2013Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 8397241Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.Type: GrantFiled: December 30, 2008Date of Patent: March 12, 2013Assignee: Intel CorporationInventors: Zhou Xiaocheng, Shoumeng Yan, Ying Gao, Hu Chen, Peinan Zhang, Mohan Rajagopalan, Avi Mendelson, Bratin Saha
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Publication number: 20110273535Abstract: A mole monitoring system comprising an imaging station adapted to record at least two temporally-distinct images of a mole, wherein said imaging station comprises an interface module adapted to transmit said images to a remote storage device; and control logic adapted to retrieve said images from said remote storage device and to compare a parameter across said at least two images of said mole, wherein a difference in the parameter is indicative of the mole being potentially associated with melanoma.Type: ApplicationFiled: January 28, 2009Publication date: November 10, 2011Inventor: Avi Mendelson
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Publication number: 20100217161Abstract: A system for delivering ultrasonic focused energy, the system comprising a transducer unit for delivering the ultrasonic focused energy, the transducer unit comprising an interface medium adapted to contact at least a portion of a treatment region in a treatment area, and further comprising an electromagnetic (EM) radiating element adapted to transmit EM radiation towards the interface medium, wherein a reflection of the EM radiation from the interface medium is indicative of an extent of acoustic contact; and an energy processing unit adapted to send electrical energy to the transducer unit.Type: ApplicationFiled: February 25, 2009Publication date: August 26, 2010Inventors: Avi Shalgi, Avi Mendelson
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Publication number: 20100122264Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.Type: ApplicationFiled: December 30, 2008Publication date: May 13, 2010Inventors: Zhou Xiaocheng, Shoumeng Yan, Ying Gao, Hu Chen, Peinan Zhang, Mohan Rajagopalan, Avi Mendelson, Bratin Saha
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Publication number: 20100118041Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.Type: ApplicationFiled: December 30, 2008Publication date: May 13, 2010Inventors: Hu Chen, Ying Gao, Zhou Xiaocheng, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
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Publication number: 20100063403Abstract: A method and an apparatus adapted to perform three dimensional (3D) position-tracking of a transducer unit comprising a three dimensional (3) target, the 3D target adapted to show a position of the transducer unit, and further adapted to facilitate tracking a tilt angle of the transducer unit; and an optical imager adapted to acquire a two dimensional (2D) target image of the target.Type: ApplicationFiled: September 8, 2008Publication date: March 11, 2010Inventor: Avi Mendelson
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Patent number: 7586281Abstract: Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.Type: GrantFiled: July 24, 2006Date of Patent: September 8, 2009Assignee: Intel CorporationInventors: Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy
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Patent number: 7558946Abstract: In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.Type: GrantFiled: December 12, 2005Date of Patent: July 7, 2009Assignee: Intel CorporationInventors: Avi Mendelson, Michael Mishaeli, Julius Mandelblat
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Patent number: 7451333Abstract: Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.Type: GrantFiled: September 3, 2004Date of Patent: November 11, 2008Assignee: Intel CorporationInventors: Alon Naveh, Abraham Avi Mendelson, Ittai Anati, Eliezer Weissmann
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Publication number: 20070150703Abstract: In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.Type: ApplicationFiled: December 12, 2005Publication date: June 28, 2007Inventors: Avi Mendelson, Michael Mishaeli, Julius Mandelblat
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Publication number: 20070124736Abstract: Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non- idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.Type: ApplicationFiled: November 28, 2005Publication date: May 31, 2007Inventors: Ron Gabor, Gad Sheaffer, Avi Mendelson, Uri Weiser, Hong Wang