Abstract: A system may include one or more processors. The one or more processors may be configured to determine, using first data relating to a sample set of non-volatile memory devices, one or more program parameters of each of a plurality of rows of cells of a non-volatile memory. The one or more processors may be configured to adjust, using the first data, the one or more program parameters of each of the plurality of rows by equalizing the one or more program parameters across the plurality of rows. The one or more processors may be configured to determine one or more programming voltages of each row based at least in part on the adjusted program parameters of the plurality of rows. The one or more processors may be configured to program a first row of the plurality of rows using the one or more programming voltages of the first row.

Abstract: In some embodiments, a flash memory system may include a non-volatile memory, a controller, a first processor, and a second processor. The first processor may generate a first configuration including a pointer to a first set of predefined configurations among a plurality of predefined configurations. In response to generating the first configuration, the circuit may generate, in a memory, the first set of predefined configurations. The controller may execute a first operation according to the first set of predefined configurations generated in the memory. The second processor may generate a second configuration comprising a pointer to a second set of predefined configurations among the plurality of predefined configurations. In response to generating the second configuration, the controller may generate, in the memory, the second set of predefined configurations. The controller may execute a second operation according to the second set of predefined configurations generated in the memory.

Abstract: The present disclosure relates to a flash memory system may include a non-volatile memory and a circuit. The non-volatile memory may include one or more blocks, each block including a plurality of rows of cells. The circuit for performing operations on the non-volatile memory, may obtain a row identifier identifying a row of a target page, among the plurality of rows. The circuit may generate, by a machine learning model, one or more voltage thresholds for a read operation, based on the row identifier. The circuit may perform the read operation on the target page of the non-volatile memory with the one or more voltage thresholds.

Abstract: A method for dynamically estimating interference compensation thresholds of a page of memory includes performing a mock read on a target row using a mock read threshold, performing a read operation on an interference source and reading an interference state of the interference source, computing a histogram and a corresponding threshold based on the mock read threshold and the interference state of the interference source, and estimating a read threshold to dynamically compensate the interference state of the target row based on the histogram.

Abstract: One or more processors of a system may determine one or more program parameters of a plurality of rows of cells of a non-volatile memory, determine a first threshold of a first parameter of each row based on the one or more program parameters of the plurality of rows, determine, by changing a programming time of each row, a set of parameters of each row that causes the first parameter not to cross the first threshold, determine a second threshold of a second parameter of each row based on production statistics of a plurality of dies as a result of mass production, adjust the programming time of each row to cause the second parameter not to cross the second threshold, and program data to a first row of the plurality of rows using the set of parameters of the first row and the adjusted programming time of the first row.

Abstract: A method for reading data from a solid-state drive (SSD) configured to store data in a plurality of memory cells arranged in memory blocks comprising rows, the method performed by a controller in communication with the plurality of memory cells. The method comprises retrieving data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages. The method also includes decoding the data using a hard decision stage. Additionally the method comprises estimating read threshold voltages of the target row of memory cells based on a transformation of a distribution of threshold voltages of cells in a memory block containing the target row when the hard decision decoding stage fails. The method further includes retrieving data from the target row using the estimated read threshold voltages.

Abstract: The present disclosure relates to systems, apparatuses, methods, and non-transitory computer-readable media including a non-volatile memory and a controller operatively coupled to the non-volatile memory. The controller is to determine information on a number of errors for a page for reading data stored in the page of the non-volatile memory, and the data is read using a first read threshold. The controller is to determine a second read threshold based at least in part on the first read threshold and the number of page errors for the page and apply the second read threshold for subsequently reading data stored on the page according to a decision rule.

Abstract: The arrangements disclosed herein relate to systems, methods, non-transitory computer-readable media, and apparatuses including a non-volatile memory and a controller operatively coupled to the non-volatile memory. The controller is to determine information on a number of errors for at least a portion of a page for performing a sequential read operation of a plurality of pages of a block of a plurality of blocks of the non-volatile memory, where the data is read using a first read threshold. The controller is to determine a second read threshold based at least in part on read histogram for the sequential read operation and the information on the number of the errors for at least the portion of the page and the first read threshold.

Abstract: One or more processors of a system may determine one or more program parameters of a plurality of rows of cells of a non-volatile memory, determine a first threshold of a first parameter of each row based on the one or more program parameters of the plurality of rows, determine, by changing a programming time of each row, a set of parameters of each row that causes the first parameter not to cross the first threshold, determine a second threshold of a second parameter of each row based on production statistics of a plurality of dies as a result of mass production, adjust the programming time of each row to cause the second parameter not to cross the second threshold, and program data to a first row of the plurality of rows using the set of parameters of the first row and the adjusted programming time of the first row.

Abstract: A system may include one or more processors. The one or more processors may be configured to determine, using first data relating to a sample set of non-volatile memory devices, one or more program parameters of each of a plurality of rows of cells of a non-volatile memory. The one or more processors may be configured to adjust, using the first data, the one or more program parameters of each of the plurality of rows by equalizing the one or more program parameters across the plurality of rows. The one or more processors may be configured to determine one or more programming voltages of each row based at least in part on the adjusted program parameters of the plurality of rows. The one or more processors may be configured to program a first row of the plurality of rows using the one or more programming voltages of the first row.

Abstract: One or more processors of a system may determine one or more program parameters of a plurality of rows of cells of a non-volatile memory, determine a first threshold of a first parameter of each row based on the one or more program parameters of the plurality of rows, determine, by changing a programming time of each row, a set of parameters of each row that causes the first parameter not to cross the first threshold, determine a second threshold of a second parameter of each row based on production statistics of a plurality of dies as a result of mass production, adjust the programming time of each row to cause the second parameter not to cross the second threshold, and program data to a first row of the plurality of rows using the set of parameters of the first row and the adjusted programming time of the first row.

Abstract: Embodiments relate to decoding data read from a non-volatile storage device, including determining error candidates for the data based on component codes, determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate, determining whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate in response to implementing a suggested correction at one of the error candidates, and correcting errors in the data based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

Abstract: A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

Abstract: Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.

Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Abstract: Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.

Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include generating the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.