Patents by Inventor Avi Urman
Avi Urman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20260089099Abstract: Methods, apparatuses, and computer program products are provided for processing data packets. The method includes receiving a data packet. The method further includes matching the data packet to a steering table entry (STE), wherein the STE includes arguments associated with processing the data packet and a pointer that points to an executable sequence. The method further includes dynamically configuring the executable sequence to process the data packet using at least the arguments. The method further includes executing the executable sequence to process the data packet.Type: ApplicationFiled: September 24, 2024Publication date: March 26, 2026Applicant: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi URMAN, Ariel SHAHAR, Najeeb DARAWSHY
-
Publication number: 20260079839Abstract: A network device includes a programmable core and a hardware pipeline having a parser engine to parse and retrieve information from a network packet and a set of hardware engines coupled to the parser engine. The set of hardware engines is to determine a packet-processing action to be performed based on the retrieved information and send an action request to the programmable core to trigger the programmable core to execute a hardware thread to perform a job. The job is associated with the packet-processing action and generates contextual data. The set of hardware engines retrieves and integrates the contextual data into performing the packet-processing action.Type: ApplicationFiled: June 26, 2025Publication date: March 19, 2026Inventors: Omri Kahalon, Avi Urman, Ilan Pardo, Omer Cohen, Sayantan Sur, Barak Biber, Saar Tarnopolsky, Ariel Shahar
-
Publication number: 20260067220Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to (i) identify a memory-access congestion, which is caused by one or more of the processing tasks attempting to access the shared memory in a manner that exceeds an access capability of the shared memory, and (ii) in response to identifying the memory-access congestion, alleviate the memory-access congestion by causing a reduction in a communication rate of at least one outgoing packet flow, among the one or more packet flows, that is sent from the network device to a selected destination.Type: ApplicationFiled: November 11, 2025Publication date: March 5, 2026Inventors: Michael Weiner, Amit Hermony, Avi Urman, Idan Burstein, Yuval Shpigelman
-
Publication number: 20260039727Abstract: A network device includes a packet processing pipeline and handoff circuitry. The packet processing pipeline is to apply to a packet a sequence of commands, one of the commands being a handoff command that diverts processing of the packet to an external device. The handoff circuitry is to generate, in response to the handoff command, an output context indicative of a current processing state of the packet, to send the output context to the external device, to receive from the external device an input context that (i) reflects the processing applied to the packet by the external device and (ii) specifies subsequent processing of the packet by the packet processing pipeline, and to forward the input context to the packet processing pipeline.Type: ApplicationFiled: August 4, 2024Publication date: February 5, 2026Inventors: Tsahi Daniel, Idan Burstein, Avi Urman, Santhanakrishnan Geeyarpuram
-
Publication number: 20260019361Abstract: In one embodiment, a network device includes a network interface to receive first packets from a network and send second packets over the network, a processing unit to execute software handlers, an input-output buffer to store data used by the processing unit, and packet processing hardware to parse a header of a packet and maintain metadata of the packet, determine an action to be performed for the packet including calling a given software handler, transfer at least one region of the metadata to the input-output buffer based on a handler configuration of the given software handler, and call the given software handler to perform processing associated with the packet, wherein the processing unit is to execute the given software handler, which is to perform processing based on the transferred at least one region of the metadata.Type: ApplicationFiled: July 14, 2024Publication date: January 15, 2026Inventors: Istvan Haller, Omri Kahalon, Krishna Garlapati, Stephen Warren, Avi Urman
-
Publication number: 20250392548Abstract: Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.Type: ApplicationFiled: August 27, 2025Publication date: December 25, 2025Applicant: MELLANOX TECHNOLOGIES, LTD.Inventors: Michael WEINER, Avi URMAN, Gary MATAEV, Idan BURSTEIN
-
Patent number: 12500840Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.Type: GrantFiled: April 27, 2023Date of Patent: December 16, 2025Assignee: Mellanox Technologies, LtdInventors: Michael Weiner, Amit Hermony, Avi Urman, Idan Burstein, Yuval Shpigelman
-
Publication number: 20250358348Abstract: In one embodiment, a network device includes an interface to receive packets over a network, a parser engine to receive data of a header section of a packet, and parse at least one first part of the header section yielding first parsed data, and a steering engine to receive the first parsed data, generate a parsing information for use in parsing at least one second part of the header section, and provide the parsing information to the parser engine, wherein: the parser engine is to parse the at least one second part of the header section based on the parsing information yielding second parsed data, and the steering engine is to perform an action based on the second parsed data.Type: ApplicationFiled: May 16, 2024Publication date: November 20, 2025Inventors: Avi Urman, Doron Shriki, Amir Sharaffy, Nofit Bitton
-
Publication number: 20250358347Abstract: In one embodiment, a network device includes parser configuration registers, hardware parsers coupled to receive data of a header section of a packet and including flexible hardware parsers to parse the data of the header section based on parser configurations loaded into the parser configuration registers, and a controller to selectively load the parser configurations associated with different protocols into the parser configuration registers such that a next parser configuration is loaded into the parser configuration registers based on a next protocol found while parsing a previous header of the header section.Type: ApplicationFiled: May 16, 2024Publication date: November 20, 2025Inventors: Avi Urman, Amir Sharaffy, Hillel Chapman
-
Patent number: 12425343Abstract: Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.Type: GrantFiled: July 28, 2022Date of Patent: September 23, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Michael Weiner, Avi Urman, Gary Mataev, Idan Burstein
-
Patent number: 12425357Abstract: Apparatuses, systems, and techniques to eliminate redundant data packets. In at least one embodiment, a communication apparatus generates redundant data packets, and sends them in multiple packet streams. In at least one embodiment, a communication apparatus eliminates redundant data packets from received packet streams.Type: GrantFiled: August 23, 2021Date of Patent: September 23, 2025Assignee: MELLANOX TECHNOLOGIES LTD.Inventors: Avi Urman, Lior Narkis, Gil Kremer, Saar Tarnopolsky, Dotan David Levi
-
Publication number: 20250286828Abstract: A network device includes a hardware-implemented packet processing pipeline includes: multiple pipeline stages, and a processor. The hardware-implemented packet processing pipeline is to process packets exchanged with a packet network. The processor is to execute sideband tasks for the packet processing pipeline. At least one of the pipeline stages is to trigger the processor to execute a sideband task by posting a Completion-Queue Element (CQE) on a Completion Queue (CQ) accessible to the processor.Type: ApplicationFiled: March 2, 2025Publication date: September 11, 2025Inventors: Yuval Shpigelman, Elazar Cohen, Yamin Friedman, Ariel Shahar, Roee Moyal, Shay Aisman, Avi Urman, Doron Haim, Saar Tarnopolsky, Amir Sharaffy
-
Patent number: 12360894Abstract: A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.Type: GrantFiled: October 3, 2022Date of Patent: July 15, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Omri Kahalon, Avi Urman, Ilan Pardo, Omer Cohen, Sayantan Sur, Barak Biber, Saar Tarnopolsky, Ariel Shahar
-
Publication number: 20250217148Abstract: A device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The match-action circuitry is to provide the instruction processor information for performing the programmable action.Type: ApplicationFiled: March 20, 2025Publication date: July 3, 2025Inventors: Ariel Shahar, Avi Urman, Omri Kahalon, Uria Basher, Doron Haim, Sagi Farjun
-
Patent number: 12339784Abstract: An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.Type: GrantFiled: August 14, 2022Date of Patent: June 24, 2025Assignee: Mellanox Technologies, LtdInventors: Gal Yefet, Yamin Friedman, Daniil Provotorov, Ariel Shahar, Natan Oppenheimer, Ran Avraham Koren, Avi Urman
-
Publication number: 20250175531Abstract: Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.Type: ApplicationFiled: January 23, 2025Publication date: May 29, 2025Applicant: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi URMAN, Ariel SHAHAR, Najeeb DARAWSHY
-
Patent number: 12282775Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.Type: GrantFiled: May 22, 2023Date of Patent: April 22, 2025Assignee: Mellanox Technologies, LtdInventors: Ariel Shahar, Avi Urman, Omri Kahalon, Uria Basher, Doron Haim, Sagi Farjun
-
Patent number: 12255734Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.Type: GrantFiled: October 26, 2022Date of Patent: March 18, 2025Assignee: Mellanox Technologies, LtdInventors: Wojciech Wasko, Dotan David Levi, Avi Urman, Natan Manevich
-
Publication number: 20250080616Abstract: Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.Type: ApplicationFiled: September 6, 2023Publication date: March 6, 2025Applicant: Mellanox Technologies, Ltd.Inventors: Avi URMAN, Ariel SHAHAR, Najeeb DARAWSHY
-
Patent number: 12244671Abstract: Apparatus and method for improved network resource management are described herein. An example computing apparatus comprises a network adapter configured to: receive, via a network connection, a data packet from the communication network; determine, from the first memory block, a value of an extended portion of a local counter associated with the network connection in response to receiving the data packet; capture, from the second memory block, a value of a global counter; compare the value of the extended portion of the local counter with the value of the global counter; and in an instance in which the comparison identifies a mismatch: update the value of the extended portion of the local counter based on the value of the global counter; and set a current value of a bit indicating a status of the network connection, wherein the bit is associated with the plurality of bits.Type: GrantFiled: September 6, 2023Date of Patent: March 4, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Avi Urman, Ariel Shahar, Najeeb Darawshy