Abstract: A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events. Future directed checks are fixed-up by either repeating a failed check with a concatenation of the current segment and a next segment, or by providing an overlap between segments to ensure that the expected time duration between a causative event and the resulting event are included within the same segment file.

Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.

Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.

Abstract: A method, apparatus, and product for partial instruction-by-instruction checking on acceleration platforms. The method comprising: obtaining a trace from an hardware accelerator, wherein the trace is generated by the hardware accelerator during simulation of an execution of a test case on a circuit design; identifying a synchronization point in the trace; simulating execution of the test case by a reference model until reaching the synchronization point; and performing instruction-by-instruction checking in order to identify an error in the circuit design based on the simulated execution by the hardware accelerator, wherein the instruction-by-instruction checking is performed with respect to a portion of the trace that relates to operation after executing the synchronization point, wherein the instruction-by-instruction checking utilizes the reference model to determine an expected outcome of each event recorded in the portion of the trace.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.

Abstract: An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Abstract: A method, apparatus and product for generating elements based on generation streams. The method comprises: obtaining one or more generation streams, wherein the streams comprise elements, wherein each element is a formal specification of an operation that stimulates a system, wherein based on each of the generation streams one or more alternative stimuli for the system can be generated, which stimuli comprises operations according to the elements; and generating a stimuli in accordance with the one or more generation streams, wherein the stimuli comprises at least one hybrid operation, wherein the hybrid operation complies simultaneously with two or more elements of the one or more generation stream, whereby the stimuli is comprised of a number of operations that is smaller than a sum of the numbers of elements of the one or more generation streams.

Abstract: A method, apparatus and product. The method comprising automatically determining an abstract CSP based on a formally defined problem having interconnected sub-problems, wherein the abstract CSP corresponds to the problem, wherein the abstract CSP has a reduced complexity in comparison to a CSP representing the problem, wherein the abstract CSP captures the interconnection between the sub-problems and reduces the details of each sub-problem, wherein the abstract CSP comprises constraints over variables, wherein each variable having an associated domain; and repeatedly: (1) propagating constraints of the abstract CSP to reduce domains of the abstract CSP; (2) selecting a sub-problem to solve; (3) solving the sub-problem; and (4) updating the abstract CSP with values in accordance with the solution of the sub-problem. Whereby, a solution to the formally defined problem is determined based on the solutions to the sub-problems.

Abstract: A CSP is modified to include an auxiliary variable. A component of a constraint of the CSP is modified to refer to the auxiliary variable instead of referring to a pair of variables. A domain for the auxiliary variable may be defined based on domains of the pair of variables. A binding constraint is added to the CSP to bind the value of the auxiliary variable with the values of the pair of variables. The modified CSP is solved using a CSP solver.

Abstract: Coverage analysis may be performed using reverse time. The coverage analysis may be based on last hit data. The last hit data may comprise a timestamp indicating a last time in which a coverage event was covered. Utilizing last hit data instead of first hit data as is known in the art enables distinction between coverage goals that were never covered and coverage goals that were not covered lately.

Abstract: Systems and methods for modeling test space for verifying system behavior, using one or more auxiliary variables, are provided. The method comprises implementing a functional coverage model including: one or more attributes, wherein respective values for the attributes are assigned according to a test plan, and one or more constraints defining restrictions on value combinations assigned to the attributes, wherein the restrictions are Boolean expressions defining whether said value combinations are valid; determining a set of valid value combinations for the attributes that satisfy the restrictions to define the test space for verifying the system behavior; and determining relevant auxiliary variables and a corresponding function for said auxiliary variables to reduce the complexity associated with modeling the test space.

Abstract: a computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.

Abstract: A CSP is modified to include an auxiliary variable. A component of a constraint of the CSP is modified to refer to the auxiliary variable instead of referring to a pair of variables. A domain for the auxiliary variable may be defined based on domains of the pair of variables. A binding constraint is added to the CSP to bind the value of the auxiliary variable with the values of the pair of variables. The modified CSP is solved using a CSP solver.

Abstract: An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Abstract: Apparatus for presentation of functional coverage, including one or more processors and a memory, wherein the memory stores software instructions including instructions for representing a set of attributes of a design under test as a multi-dimensional cross-product space, comprising events corresponding to combinations of values of the attributes to be tested, the events comprising legal and illegal events, instructions for running at least one test on the design, instructions for identifying, responsively to the at least one test, a first group of the legal events that were covered by the at least one test and a second group of the legal events that remain non-covered after the at least one test, instructions for grouping one or more of the illegal events with at least one of the first and second groups so as to generate a simplified model of the functional coverage of the events in the cross-product space and instructions for presenting the simplified model of the functional coverage on an output device.

Abstract: Coverage analysis may be performed using reverse time. The coverage analysis may be based on last hit data. The last hit data may comprise a timestamp indicating a last time in which a coverage event was covered. Utilizing last hit data instead of first hit data as is known in the art enables distinction between coverage goals that were never covered and coverage goals that were not covered lately.

Abstract: Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatically constructed and executed on the test results to identify a hole in the functional coverage that satisfies conditions of the coverage query and includes the core set. The results of the query are presented as a simplified view of the coverage of the events in the cross-product space. Use of coverage queries allows a verification team to focus on specific areas of interest in the coverage space and to deal practically with highly complex coverage models. It also avoids the burden of producing and evaluating complete hole analysis reports.

Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.

Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.