Abstract: A PHY for transmitting link frames on a home phone line network without the need of a MAC layer. The PHY transmits an initial link frame if the PHY has not transmitted a frame for a time interval, as specified by the Home Phoneline Networking Alliance. After transmission of the initial link frame, the transmit-clock signal to the MAC is disabled so that the MAC does not request the PHY to transmit a frame. If a collision is detected during transmission of the initial link frame, a counter is set to zero and the PHY transmits back-to-back link frames, where the initial link frame and the back-to-back link frames are each separated by an IPG (Inter Packet Gap). When transmitting these back-to-back link frames, the counter is incremented each time a collision is detected. When the counter equals a specified number, the transmit-clock signal to the MAC is enabled and the PHY waits for a random interval of time before beginning the above-described process again.

Abstract: A multi-MAC chip for an Ethernet, the multi-MAC chip generating different random variables for each MAC layer so that each MAC has a distinct backoff interval when there is a collision. This avoids a possible live-lock state. In one embodiment, the random variables are generated by adding distinct numbers to a random variable generated according to the truncated binary exponential backoff algorithm. In another embodiment, each MAC stops a free-running counter for some specified number of clock cycles upon occurrence of a distinct event, and each counter for each colliding MAC is sampled upon a collision to provide random integers used to calculate backoff intervals for each colliding MAC.

Abstract: A system and method are presented for multiplexing two or more clocking signals. In one embodiment, a first enable circuit is provided that receives a select signal, a first clocking signal, and an enable signal from a second enable circuit. The first enable circuit generates an enable signal in response to these signals. For example, the first enable circuit could include a flip-flop clocked by the first clocking signal that generates the enable signal when the first clocking signal has been selected (based on the select signal), when the enable signal from the second enable circuit is deasserted and the first clocking signal has reached a falling edge. The enable signal can then be used to filter the first clocking signal (e.g., using an AND gate) to provide the first clocking signal as an output signal. Using the system and method of the present invention, glitches and spikes seen when multiplexing two or more clocking signals can be avoided.

Abstract: A system and method are presented for multiplexing two or more clocking signals. In one embodiment, a first enable circuit is provided that receives a select signal, a first clocking signal, and an enable signal from a second enable circuit. The first enable circuit generates an enable signal in response to these signals. For example, the first enable circuit could include a flip-flop clocked by the first clocking signal that generates the enable signal when the first clocking signal has been selected (based on the select signal), when the enable signal from the second enable circuit is deasserted and the first clocking signal has reached a falling edge. The enable signal can then be used to filter the first clocking signal (e.g., using an AND gate) to provide the first clocking signal as an output signal. Using the system and method of the present invention, glitches and spikes seen when multiplexing two or more clocking signals can be avoided.