Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.

Abstract: A network device includes processing circuitry and one or more ports. The one or more ports are configured to connect to a communication network. The processing circuitry is configured to receive a packet originating from a network node running an application program, the packet includes application-level metadata relating to the application program, to generate telemetry data based at least on the application-level metadata, and to transmit the telemetry data via one of the ports, over the communication network.

Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.

Abstract: A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.

Abstract: A network device includes processing circuitry and one or more ports. The one or more ports are configured to connect to a communication network. The processing circuitry is configured to receive a packet originating from a network node running an application program, the packet includes application-level metadata relating to the application program, to generate telemetry data based at least on the application-level metadata, and to transmit the telemetry data via one of the ports, over the communication network.

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

Abstract: A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

Abstract: A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.