Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Generally, this disclosure describes techniques for buffer management based on link status. A host platform may include a Baseboard Management Controller (BMC) and a network controller that includes a buffer used by the BMC. When a network controller is in a lower power link state, the BMC may attempt to send data to the link partner which causes the network controller to transition out of the low power state. However, this transition may take longer than the buffer's ability to buffer the incoming flow from the BMC. Accordingly, to avoid the need for larger buffer space, a buffer manager is used to provide flow control management of the buffer based on link status.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Methods, apparatus and systems for implementing run-time fabric reconfiguration are described herein. In accordance with one aspect, techniques are disclosed for implementing run-time fabric reconfiguration on a System on a Chip (SoC) via use of multiple endpoint fabric interfaces having routing logic that is dynamically reconfigured at run-time by a fabric control unit in response to system-state changes. The endpoint fabric interfaces may be coupled to or integrated in IP blocks that are coupled to a switch fabric, or may be implemented in the switch fabric itself. The run-time fabric reconfiguration techniques may be implemented to for various purposes and/or to address various events, such as node failures, security events, IP or design bugs, feature prototyping, and virtualization.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Generally, this disclosure describes techniques for buffer management based on link status. A host platform may include a Baseboard Management Controller (BMC) and a network controller that includes a buffer used by the BMC. When a network controller is in a lower power link state, the BMC may attempt to send data to the link partner which causes the network controller to transition out of the low power state. However, this transition may take longer than the buffer's ability to buffer the incoming flow from the BMC. Accordingly, to avoid the need for larger buffer space, a buffer manager is used to provide flow control management of the buffer based on link status.

Abstract: Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a plurality of data segments of a data bus with a source clock signal, and transmit respective synchronized data segments to individual destination modules. The source module is further configured to transmit the source clock signal to the destination modules contemporaneously with the synchronized data segments. The source module thereafter receives feedback clock signals from the individual destination modules, the feedback clock signals being delayed versions of the source clock signal. The data alignment controller adjusts an output delay time for the individual destination modules, based on the received feedback clock signals, to temporally align output signals of the destination modules.

Abstract: An embodiment may include circuitry to determine at a first hierarchy level of a compute hierarchy, whether to consolidate, at least in part, respective workloads of respective compute entities at the first hierarchy level. The respective workloads may involve one or more respective processes of the respective compute entities. The circuitry may determine whether to consolidate, at least in part, the respective workloads based at least in part upon whether at least one migration condition involving at least one of the one or more respective processes is satisfied. After determining whether to consolidate, at least in part, the respective workloads, the circuitry may determine at a second hierarchy level of the compute hierarchy, whether to consolidate, at least in part, other respective workloads of other respective compute entities at the second hierarchy level. The second hierarchy level may be relatively lower in the compute hierarchy than the first hierarchy level.

Abstract: Methods, apparatus and systems for implementing run-time fabric reconfiguration are described herein. In accordance with one aspect, techniques are disclosed for implementing run-time fabric reconfiguration on a System on a Chip (SoC) via use of multiple endpoint fabric interfaces having routing logic that is dynamically reconfigured at run-time by a fabric control unit in response to system-state changes. The endpoint fabric interfaces may be coupled to or integrated in IP blocks that are coupled to a switch fabric, or may be implemented in the switch fabric itself. The run-time fabric reconfiguration techniques may be implemented to for various purposes and/or to address various events, such as node failures, security events, IP or design bugs, feature prototyping, and virtualization.

Abstract: Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a plurality of data segments of a data bus with a source clock signal, and transmit respective synchronized data segments to individual destination modules. The source module is further configured to transmit the source clock signal to the destination modules contemporaneously with the synchronized data segments. The source module thereafter receives feedback clock signals from the individual destination modules, the feedback clock signals being delayed versions of the source clock signal. The data alignment controller adjusts an output delay time for the individual destination modules, based on the received feedback clock signals, to temporally align output signals of the destination modules.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.