Patents by Inventor Avidan Akerib
Avidan Akerib has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12650814Abstract: A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null-read result.Type: GrantFiled: March 21, 2022Date of Patent: June 9, 2026Assignee: GSI Technology Inc.Inventors: Lee-Lean Shu, Dan Ilan, Tomer Sery, Avidan Akerib
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Patent number: 12646564Abstract: A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.Type: GrantFiled: October 28, 2024Date of Patent: June 2, 2026Assignee: GSI Technology Inc.Inventors: Avidan Akerib, Eli Ehrman
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Publication number: 20260072916Abstract: A method for determining a K-Nearest Neighbor (KNN) graph for a dataset of full dimension vectors includes, for each record in a database of full dimension vectors, performing a K-Nearest Neighbor (KNN) search to locate W nearest neighbors of the record; and updating a KNN graph to include an index of the record and W indices of the W nearest neighbors located for the record. The updating includes creating a first node for the record, the first node comprising an index of the record, and creating W second-level nodes, each second-level node comprising an index of one of the W nearest neighbors.Type: ApplicationFiled: November 17, 2025Publication date: March 12, 2026Inventor: Avidan AKERIB
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Publication number: 20250378199Abstract: A system includes a secure, in-memory unit implemented on an associative processing unit (APU) for performing a secure similarity search. The unit implements a decryptor, an encoded vector store and a similarity searcher. The decryptor decrypts an encrypted, encoded vector into an encoded vector. The encoded vector data store stores a plurality of encoded search candidate vectors. The similarity searcher performs a similarity search between an encoded search query vector and the plurality of encoded search candidate vectors.Type: ApplicationFiled: July 8, 2025Publication date: December 11, 2025Inventors: Mark WRIGHT, Avidan AKERIB
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Publication number: 20250377898Abstract: A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation.Type: ApplicationFiled: August 24, 2025Publication date: December 11, 2025Inventor: Avidan AKERIB
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Patent number: 12488002Abstract: An associative graph search system includes a KNN graph determiner to determine in advance W neighbors of each item in a dataset and to store each item and its neighbors in a KNN graph, a reduced dimension vector finder implemented on an associative processing unit (APU) to find a first number of first nearest neighbors of a query vector, the APU operating in a constant complexity irrespective of the size of the number, a result expander to find for each first nearest neighbor, W second nearest neighbors using the KNN graph thereby creating a group of neighbors, and a KNN full dimension vector re-ranker to find a final number of full dimension nearest neighbors of the full dimension query vector from the group of neighbors.Type: GrantFiled: May 3, 2022Date of Patent: December 2, 2025Assignee: GSI Technology Inc.Inventor: Avidan Akerib
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Publication number: 20250348553Abstract: A system and method for single cycle binary matrix multiplication in neural network computations is disclosed. The system includes a memory array storing binary weights, an input unit for activating rows based on a binary activation vector, and per-column majority sense amplifiers. The system performs binary matrix multiplication in a single cycle, enabling efficient implementation of binary neural networks. The memory array may include sections for weights and inverse weights, with corresponding activation register sections. Differential sense amplifiers may implement the majority function. The system can be applied to convolutional neural networks, using SRAM arrays for image storage and processing. Methods for determining majority votes and counting activated bits using iterative modification of the activation vector are also described.Type: ApplicationFiled: May 6, 2025Publication date: November 13, 2025Inventors: Avidan Akerib, Eli Ehrman, Bob Haig, Lee-Lean Shu
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Publication number: 20250348681Abstract: A system for natural language processing includes a memory array and a processor. The memory array is divided into a similarity section storing a plurality of feature vectors, a SoftMax section in which to determine probabilities of occurrence of the feature vectors, a value section storing a plurality of modified feature vectors, and a marker section. The processor activates the array to perform parallel operations in each column indicated by the marker section: a similarity operation in the similarity section between a vector question and feature vectors stored in indicated columns; a SoftMax operation in the SoftMax section to determine an associated SoftMax probability value for indicated feature vectors; a multiplication operation in the value section to multiply the associated SoftMax value by modified feature vectors stored in indicated columns; and a vector sum in the value section to accumulate an attention vector of output of the multiplication operation.Type: ApplicationFiled: July 21, 2025Publication date: November 13, 2025Inventor: Avidan AKERIB
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Publication number: 20250342275Abstract: A system includes a secure, in-memory unit implemented on an associative processing unit (APU) for performing a secure similarity search. The unit implements a decryptor, a neural proxy hash encoder, an encoded vector store and a similarity searcher. The decryptor decrypts an encrypted data vector into a data vector. The neural proxy hash encoder encodes the data vector into an encoded search data vector. The encoded vector data store stores a plurality of encoded search candidate vectors and the similarity searcher performs a similarity search between an encoded search query vector and the plurality of encoded search candidate vectors.Type: ApplicationFiled: July 8, 2025Publication date: November 6, 2025Inventors: Mark WRIGHT, Avidan AKERIB
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Patent number: 12423112Abstract: A unit for accumulating a plurality of multiplied bit values includes a first row and a second row of input units, a bit-wise multiplier and a bit-wise accumulator. The first row receives a pipeline of the bits of a multiplicand A and the second row, to the left of the first row, receives a pipeline of the bits of a multiplicand B. The bit-wise multiplier, below the first row of input units, includes multiplier bit-line processors formed into rows and columns. Some rows of the bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with one bit of a current multiplicand B and some rows of the bit-wise multiplier handle sum and carry values between the bits. The bit-wise accumulator, to the right of the bit-wise multiplier, includes a column of accumulator bit-line processors. Each accumulator bit-line processor accumulates output of a row of the bit-wise multiplier.Type: GrantFiled: February 18, 2024Date of Patent: September 23, 2025Assignee: GSI Technology Inc.Inventor: Avidan Akerib
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Publication number: 20250272857Abstract: A system to refine segmented image categories includes a pixel feature set extractor, a known sub-category database, a pixel feature set searcher and a sub-category assignor. The extractor extracts pixel level feature sets corresponding to segmented image blocks, the segmented image blocks having data and category metadata. The known sub-category database stores known sub-category feature sets extracted from segmented images with known sub-categories. The pixel feature set searcher matches query pixel feature sets to candidate known sub-category feature sets using a similarity search and the sub-category assigner adds sub-category metadata to the segmented image block metadata.Type: ApplicationFiled: May 14, 2025Publication date: August 28, 2025Inventors: Elona EREZ, Avidan AKERIB
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Publication number: 20250272856Abstract: A system to align two images includes a feature set database, an anchor block searcher, an image aligner, and a block tabulator. The feature set database stores candidate feature sets extracted from image blocks of a first image, and the anchor block searcher identifies anchor blocks by searching for the candidate feature sets that match a query feature set extracted from an image block from a second image, using a similarity search. The image aligner aligns the anchor blocks in the first image and the anchor blocks in the second image, hence aligning the first image and the second image, and the block tabulator correlates and tabulates image blocks from the first aligned image and image blocks from the second aligned image.Type: ApplicationFiled: May 14, 2025Publication date: August 28, 2025Inventors: Elona EREZ, Avidan AKERIB
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Patent number: 12387002Abstract: A system including a secure, in-memory unit implemented on an associative processing unit (APU), for creating encrypted vectors. The in-memory unit includes a data store and an encryptor. The data store stores data and the encryptor encrypts the data into an encrypted vector. Optionally, the unit includes a neural proxy hash encoder that encodes the data into an encoded vector, and, in this embodiment, the encryptor encrypts the encoded vector into an encrypted encoded vector. The neural proxy hash encoder includes a trained neural network which includes a plurality of layers that encode the data into feature sets. The trained neural network encodes image files, audio files, or large data sets. The APU is implemented on SRAM, non-volatile, or non-destructive memory.Type: GrantFiled: May 9, 2021Date of Patent: August 12, 2025Assignee: GSI Technology Inc.Inventors: Mark Wright, Avidan Akerib
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Patent number: 12367346Abstract: A system for natural language processing includes a memory array and a processor. The memory array is divided into a similarity section storing a plurality of feature vectors, a SoftMax section in which to determine probabilities of occurrence of the feature vectors, a value section storing a plurality of modified feature vectors, and a marker section. The processor activates the array to perform parallel operations in each column indicated by the marker section: a similarity operation in the similarity section between a vector question and feature vectors stored in indicated columns; a SoftMax operation in the SoftMax section to determine an associated SoftMax probability value for indicated feature vectors; a multiplication operation in the value section to multiply the associated SoftMax value by modified feature vectors stored in indicated columns; and a vector sum in the value section to accumulate an attention vector of output of the multiplication operation.Type: GrantFiled: July 12, 2018Date of Patent: July 22, 2025Assignee: GSI Technology Inc.Inventor: Avidan Akerib
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Publication number: 20250181560Abstract: A deduplication system includes an associative memory device with a fingerprint section which has uppermost, intermediate, and lowest levels for data block fingerprints. The uppermost and intermediate levels store centroids of fingerprint clusters in lower levels, and the lowest level stores collision-resistance (CR) fingerprints of sub-blocks. The device includes a locality-sensitive hash (LSH) fingerprint fingerprint creator for the input block, and a CR fingerprint creator for sub-blocks. If a searcher finds no similar fingerprint in the uppermost and intermediate levels, a storage manager stores the sub-blocks, stores the CR fingerprints in the lowest level and updates the centroids with the input fingerprint; otherwise, a searcher searches in the lowest level for identical fingerprints matching the CR fingerprints.Type: ApplicationFiled: February 6, 2025Publication date: June 5, 2025Inventors: Avidan AKERIB, Dan ILAN, Eli EHRMAN, Elona EREZ
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Patent number: 12322121Abstract: A system for detecting changes between two temporally different images includes an image divider, a Convolutional Neural Network (CNN) feature encoder, an image alignment system, a feature comparator, a CNN feature decoder and segmenter, and a block combiner. The image divider divides a first and second image into a plurality of image blocks. CNN feature encoder encodes the image blocks from the first and second image into first and second feature sets respectively. The image alignment system aligns the first and second image by searching for matching anchor vectors in the first and second feature sets using a similarity search. The feature comparator produces change feature sets from the first and second feature sets of the aligned image blocks, and the CNN feature decoder and segmenter creates segmented change image blocks from the change feature sets. The block combiner combines segmented change image blocks into a segmented change image.Type: GrantFiled: April 12, 2021Date of Patent: June 3, 2025Assignee: GSI Technology Inc.Inventors: Elona Erez, Avidan Akerib
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Patent number: 12259859Abstract: A deduplication system includes a similarity searcher, a difference calculator, and a storage manager. The similarity searcher searches for a similar fingerprint in a database storing a plurality of local sensitive fingerprints, resembling a new fingerprint of a new block. The difference calculator computes a difference block between the input block and a similar block associated with the found similar fingerprint, and the storage manager updates the database with the new fingerprint and stores the difference block, if not empty, in a store. A method for deduplication includes searching in a database, storing a plurality of local sensitive fingerprints, a similar fingerprint, resembling a new fingerprint of a new block, calculating a difference block between the input block and a similar block associated with the similar fingerprint, if found, updating the database with the new fingerprint and storing the difference block, if it is not empty, in a storage unit.Type: GrantFiled: June 25, 2020Date of Patent: March 25, 2025Assignee: GSI Technology Inc.Inventors: Avidan Akerib, Dan Ilan, Eli Ehrman, Elona Erez
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Publication number: 20250081474Abstract: A semiconductor package assembly includes an interposer mounted on a package substrate, a column parallel processor mounted on and electrically connected to the interposer, and a high bandwidth memory (HBM) stack mounted on the parallel processor. The parallel processor includes a memory array with rows and columns, with operations occurring in the columns. Columns of the HBM stack are electrically connected to the columns of the parallel processor. The column parallel processor includes an associative processing unit (APU), a switch fabric for managing data routing, a local SRAM for temporary storage, and a buffer for managing data flow between the HBM stack and processing elements. The assembly is configured to process large language models and perform pattern searches within large datasets stored in the HBM stack.Type: ApplicationFiled: August 21, 2024Publication date: March 6, 2025Inventors: Lee-Lean SHU, Avidan AKERIB, Bob HAIG
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Publication number: 20250054545Abstract: A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Inventors: Avidan AKERIB, Eli EHRMAN
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Patent number: 12131779Abstract: A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.Type: GrantFiled: June 5, 2023Date of Patent: October 29, 2024Assignee: GSI Technology Inc.Inventors: Avidan Akerib, Eli Ehrman