Patents by Inventor Avidan Efody

Avidan Efody has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9910943
    Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can correlate transactions captured during simulation of a circuit design to distributed states for multiple components in the circuit design. The computing system can identify at least a portion of the distributed states for the multiple components correspond to system level coverage events. The computing system can generate a graphical presentation to illustrate the portion of the distributed states for the multiple components in the circuit design that correspond to system level coverage events.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Andreas Meyer, Gustav Bjorkman, Avidan Efody
  • Patent number: 9898562
    Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can identify multiple components in the circuit design to combine for distributed state coverage analysis based, at least in part, on data transactions generated during the simulation of the circuit design. The computing system can correlate information captured during simulation that corresponds to the identified components. The correlated information can identify at least one distributed state coverage event for the test bench. The computing system can generate a distributed state coverage metric based on the correlated information corresponding to the identified components. The computing system can prompt presentation of the correlated information a display window, which can graphically show how a test bench exercised the identified components during simulation.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: February 20, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Andreas Meyer, Gustav Bjorkman, Avidan Efody
  • Publication number: 20150213173
    Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can identify multiple components in the circuit design to combine for distributed state coverage analysis based, at least in part, on data transactions generated during the simulation of the circuit design. The computing system can correlate information captured during simulation that corresponds to the identified components. The correlated information can identify at least one distributed state coverage event for the test bench. The computing system can generate a distributed state coverage metric based on the correlated information corresponding to the identified components. The computing system can prompt presentation of the correlated information a display window, which can graphically show how a test bench exercised the identified components during simulation.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: Andreas Meyer, Gustav Bjorkman, Avidan Efody
  • Publication number: 20150213170
    Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can correlate transactions captured during simulation of a circuit design to distributed states for multiple components in the circuit design. The computing system can identify at least a portion of the distributed states for the multiple components correspond to system level coverage events. The computing system can generate a graphical presentation to illustrate the portion of the distributed states for the multiple components in the circuit design that correspond to system level coverage events.
    Type: Application
    Filed: January 31, 2014
    Publication date: July 30, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: Andreas Meyer, Gustav Bjorkman, Avidan Efody
  • Patent number: 8972914
    Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Raghu Ardeishar, Richard Edelman, Avidan Efody, Allan Crone Klinck
  • Publication number: 20140123087
    Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventors: Raghu Ardeishar, Richard Edelman, Avidan Efody, Allan Crone Klinck
  • Publication number: 20130246987
    Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.
    Type: Application
    Filed: February 6, 2013
    Publication date: September 19, 2013
    Applicant: MENTOR GRAPHICS CORPORATION
    Inventors: Raghu Ardeishar, Richard Edelman, Avidan Efody, Allan Crone Klinck
  • Publication number: 20120233582
    Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.
    Type: Application
    Filed: May 23, 2012
    Publication date: September 13, 2012
    Inventors: Raghu Ardeishar, Richard Edelman, Avidan Efody, Allan Crone Klinck
  • Publication number: 20100306728
    Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.
    Type: Application
    Filed: April 19, 2010
    Publication date: December 2, 2010
    Inventors: Raghu Ardeishar, Richard Edelman, Avidan Efody, Allan Crone Klinck