Abstract: A cellular telecommunications alternative for the distribution of broadcast television for receivers that may be wireless and mobile, or for regions inaccessible to satellites but not yet wired for cablevision. A communications system for the distribution of broadcast television programming by a cellular telecommunications service provider to a plurality of service subscribers through wireless receivers of said subscribers that comprises the combination of apparatus for broadcasting said television programming, and service provider implementations for receiving said broadcasted television programming. This service provider uses cellular means for telecommunicating this television programming to each of the subscribers over a wireless RF channel respectively dedicated to each of said subscribers. There are wireless receiving apparatus at each of the subscribers for receiving said telecommunicated television programming.

Abstract: A method, apparatus, and computer instructions for processing a set of instructions in which the set of instructions includes operation codes and operands. A repeating sequence of sequential operation codes within the set of instructions is identified to form an identified sequence of operation codes. The set of instructions is compressed using the identified sequence of operation codes to form a set of compressed instructions for execution by a processor.

Abstract: Provided are data structures for use in storing data. A plurality of data structures are defined in a computer readable medium, wherein each data structure indicates a plurality of attributes and at least one function of a storage resource to store data. Policies are defined in the computer readable medium that associate data characteristics to data structures based on a correspondence of data characteristics and the attributes defined in the data structures, wherein each defined data structure is adapted to provide requirements to determine a storage resource to store associated data, and wherein the defined data structure is adapted to provide the storage resource with requirements for storing the data.

Abstract: A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into sectors such that the smallest accessible unit for an instruction set in each register can be uniquely addressed and renamed thereby providing additional effective registers for renaming.

Abstract: A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Abstract: A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

Abstract: A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line.

Abstract: The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof.

Abstract: A method and implementing computer system is provided in which an internet or web network user may invoke a hyperlink or site link listing mode to retrieve only the hyperlinks available on selected target pages rather than retrieving the entire text and graphics of the target pages. The network assembles only the available hyperlinks and associated activation code segments for presentation to the user. The user may then select from the presented hyperlinks, the most appropriate hyperlink or path in pursuit of the user's particular search goals. The hyperlink access methodology enables faster navigation through selected and more direct paths to particular search goals by selectively assembling and displaying listings of only hyperlinks of designated target pages rather than entire page presentations.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Abstract: A method and implementing system are provided in which specific byte requests made by a functional unit within a computer system effect the return of a word containing the requested byte to a register device within a CPU. The returned word is stored "as is" and without alignment, together with mask and alignment data indicative of the location of the requested byte within the stored word. Alignment relative to the requested byte is thereafter accomplished using the mask and alignment data just before use of the requested byte by the functional unit. The alignment function is thereby accomplished outside of the processor critical path which obviates the typical memory-processor mismatch delay inherent in prior art data alignment networks and substantially shortens the critical path in the memory access stage of the processor's pipeline.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Abstract: A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representing the detected instructions are then stored in queues, and marked (colored) as not having been executed. After a detected instruction has been executed and completed, the corresponding target in the queue is marked as being completed. During every clock cycle of the apparatus, the verification logic unit monitors the queues for entries (Targets) marked as completed, which are then discarded.

Abstract: A flexible pipeline for reducing performance limiting pipeline interlocks in the execution of programs. The pipeline architecture includes for each pipeline a fetch stage, a decode stage, an execution stage, a hybrid memory/execution stage, and a write back stage. When the result from the execution stage of a first pipeline is not available to a second pipeline until the write back stage of the first pipeline as a consequence of an interlock, the execution stage of the second pipeline may be delayed at least one execution cycle so that the executable functions are performed in the hybrid memory/execution stage or fourth stage of the second pipeline. The result from the execution stage is obtained either by a calculation of the effective address of a memory location or by performing arithmetic/logical unit (ALU) functions.

Abstract: An improved method and system for creating state machines in microcode. State machines are typically defined by a plurality having at least a combinations of current state, next state. Each one of the current states and next states are typically assigned unique values to distinguish them from other current states and next states, respectively. Upon an examination of the binary bit representations for the combinations, certain repetitive patterns become apparent between certain sections of the combinations. These recognized repetitive bit patterns are grouped and represented by linked lists and associated with one another to form the necessary relationship to define the represented combinations. Thus, saving memory and/or storage resources.

Abstract: An apparatus for utilizing multiple processors to render graphical objects for display including apparatus for storing in memory a list of pixel locations assigned to each of the processors, apparatus for scan converting each received graphical object into pixels, and each processor including apparatus for rendering graphical object pixels at pixel locations assigned to the processor. In addition, a method of utilizing multiple processors to render graphical objects for display including the steps of storing in memory a list of pixel locations assigned to each of the processors, scan converting each received graphical object into pixels, and each processor rendering graphical object pixels at pixel locations assigned to the processor.

Abstract: A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model. Each processor within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

Abstract: An efficient method and system within a data processing system for storing address tags are disclosed, which include a tag directory having a plurality of congruence classes, wherein each congruence class is arranged as a tree-like data structure. A portion of an address tag common to a plurality of address tags is stored in an entry within a node at a first level of a tree-like data structure corresponding to a congruence class of the directory. Portions of the plurality of address tags are stored in a node at a subsequent level of the tree-like data structure, such that all of the plurality of address tags share in common the portion stored in the entry within the node at the first level. Since a portion common to a plurality of address tags is stored only once, the memory space required to store the plurality of address tags is reduced.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Abstract: A method for rendering a graphical polygon, the polygon being defined by connecting edges surrounding a polygon interior, including the steps of computing multiple spans, each span including a portion of the polygon interior and at least one point on an edge of the polygon, computing at least one color value for each computed span, and rendering the spans on a display using the computed color values. In addition, an apparatus for rendering a graphical polygon, the polygon being defined by connecting edges surrounding a polygon interior, including apparatus for computing multiple spans, each span including a portion of the polygon interior and at least one point on an edge of the polygon, apparatus for computing at least one color value for each computed span, and apparatus for rendering the spans on a display using the computed color values.