Patents by Inventor Avik Ghosh

Avik Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943286
    Abstract: Systems, methods, and computer-readable media are disclosed for determining product attribute sequences using quantitative values and predicting product performance.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Avik Ghosh, Gokul Swamy
  • Patent number: 9865713
    Abstract: The interplay between chiral tunneling and spin-momentum locking of helical surface states leads to spin amplification and filtering in a 3D Topological Insulator (TI). Chiral tunneling across a TI pn junction allows normally incident electrons to transmit, while the rest are reflected with their spins flipped due to spin-momentum locking. The net result is that the spin current is enhanced while the dissipative charge current is simultaneously suppressed, leading to an extremely large, tunable longitudinal spin Hall angle (˜20) at the reflected end. At the transmitted end, the angle stays close to one and the electrons are completely spin polarized.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 9, 2018
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: K. M. Masum Habib, Redwan Noor Sajjad, Avik Ghosh
  • Patent number: 9570559
    Abstract: An electronic device can include a dielectric layer, and a graphene layer including a first surface located upon the dielectric layer. The electronic device can include a first electrode, a second electrode, and a third electrode each located upon the dielectric layer on a surface opposite the graphene layer. The first and second electrodes can be spaced apart along a longitudinal axis of the electronic device to define a first gap between the first and second electrodes, and the second and third electrodes are spaced apart along the longitudinal axis of the electronic device to define a second gap between the second and third electrodes. At least one of the first gap or the second gap can be angled so as to be neither parallel nor perpendicular to the longitudinal axis of the electronic device.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 14, 2017
    Assignee: University of Virginia Patent Foundation
    Inventors: Redwan Noor Sajjad, Avik Ghosh
  • Publication number: 20160351696
    Abstract: The interplay between chiral tunneling and spin-momentum locking of helical surface states leads to spin amplification and filtering in a 3D Topological Insulator (TI). Chiral tunneling across a TI pn junction allows normally incident electrons to transmit, while the rest are reflected with their spins flipped due to spin-momentum locking. The net result is that the spin current is enhanced while the dissipative charge current is simultaneously suppressed, leading to an extremely large, tunable longitudinal spin Hall angle (˜20) at the reflected end. At the transmitted end, the angle stays close to one and the electrons are completely spin polarized.
    Type: Application
    Filed: September 30, 2015
    Publication date: December 1, 2016
    Inventors: K M Masum Habib, Redwan Noor Sajjad, Avik Ghosh
  • Publication number: 20090257821
    Abstract: A device for braced frame assembly and method of using same in connecting brace members to a beam of a braced frame is presented. The braced frame connectors of the invention have a preferred application in cold formed steel frames in light-framed construction but can also be used effectively in braced frames of heavy-frame construction and can provide sufficient rigidity while adequately resisting lateral loads.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 15, 2009
    Inventors: Avik Ghosh, George Lewis Richards
  • Publication number: 20090174435
    Abstract: The invention discloses new and advantageous uses for carbon/graphene nanoribbons (GNRs), which includes, but is not limited to, electronic components for integrated circuits such as NOT gates, OR gates, AND gates, nano-capacitors, and other transistors. More specifically, the manipulation of the shapes, sizes, patterns, and edges, including doping profiles, of GNRs to optimize their use in various electronic devices is disclosed.
    Type: Application
    Filed: October 1, 2008
    Publication date: July 9, 2009
    Applicant: University of Virginia
    Inventors: Mircea R. Stan, Avik Ghosh
  • Publication number: 20060193687
    Abstract: A moment resisting connector and method of using same in connecting support members (e.g., beams and columns) of a moment frame are presented. The moment frame connectors of the invention have a preferred application in wood frames and can provide sufficient rigidity while adequately resisting lateral loads.
    Type: Application
    Filed: January 18, 2006
    Publication date: August 31, 2006
    Inventor: Avik Ghosh