Patents by Inventor Avinash Chander
Avinash Chander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991423Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: September 25, 2019Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 10790015Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: September 25, 2019Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20200188412Abstract: The present invention relates to new compounds and compositions comprising active ingredient derivatives of testosterone, and novel testosterone derivatives, novel testosterone methods, novel testosterone compositions, novel testosterone articles of manufacture of pharmaceutical preparations and novel testosterone therapeutic uses thereof.Type: ApplicationFiled: December 13, 2019Publication date: June 18, 2020Inventors: Nathan Bryson, Avinash Chander Sharma
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Publication number: 20200020392Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20200020391Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 10490267Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: December 6, 2018Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20190337975Abstract: The present invention contemplates novel neurosteroid derivative compounds, such as derivatives of ganaxolone and allopregnanolone, having improved solubility and bioavailability. The novel neurosteroid derivative compounds are characterized by the following formulas: wherein R1 is methyl or hydrogen, R2 is an ester function (R—C(O)O—), R3 is hydrogen, R4 is alpha or beta hydrogen, R5 is R—CO— or any hydrocarbon structure (R—), and wherein R (in R2 or R5) is independently selected from any structure comprising 10 carbon atoms or fewer, which is linear or branched, saturated or unsaturated, may comprise cyclic or aromatic functions within the structure, and wherein R contains no more than 1 OH or NR2, or 2 ether or thioether functions.Type: ApplicationFiled: May 3, 2019Publication date: November 7, 2019Inventors: Nathan Bryson, Avinash Chander Sharma
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Publication number: 20190108875Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 10157666Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: January 15, 2018Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20180137910Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Patent number: 9928899Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: GrantFiled: December 22, 2016Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20170348276Abstract: A nasally administered cannabinoid semi-solid or viscous liquid composition; nasal methods for administering the nasal pharmaceutical compositions; methods for manufacturing the nasal pharmaceutical compositions; and nasal methods of treating diseases treatable by the nasal pharmaceutical compositions formulated with a cannabinoid or mixtures thereof.Type: ApplicationFiled: June 2, 2017Publication date: December 7, 2017Inventors: Nathan Bryson, Avinash Chander Sharma
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Patent number: 9812191Abstract: A memory device includes: a memory array comprising a first plurality of bit cells arranged along a first column; and a negative bit line (NBL) circuit, coupled to the memory array. The NBL circuit includes: a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.Type: GrantFiled: September 29, 2016Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Avinash Chander, Yen-Huei Chen
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Publication number: 20170186750Abstract: An interconnect structure includes a lower interconnect layer, an intermediate interconnect layer, and an upper interconnect layer. First and second conductive lines in the lower interconnect layer extend generally in a first direction over a memory array region, and additional lower conductive lines in the lower interconnect layer extend generally in the first direction over a peripheral region. A first plurality of conductive line segments in the intermediate interconnect layer extend generally in the first direction over the memory array region, and additional intermediate conductive line segments in the intermediate interconnect layer extend generally in a second, perpendicular direction over the peripheral region. A second plurality of conductive line segments in the upper interconnect layer extend generally in the first direction over the memory array region, and additional upper conductive line segments in the upper interconnect layer extend generally in the first direction over the peripheral region.Type: ApplicationFiled: December 20, 2016Publication date: June 29, 2017Inventors: Sahil Preet Singh, Yen-Huei Chen, Avinash Chander
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Publication number: 20170186483Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.Type: ApplicationFiled: December 22, 2016Publication date: June 29, 2017Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
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Publication number: 20120142651Abstract: There is provided a method of treatment of allergic rhinitis which comprises administering to a patient a pharmaceutically acceptable amount of a pharmaceutical formulation comprising an aqueous suspension of particulate compound of formula (I) or a solvate thereof, wherein the administration is once-per-day and intranasal, and the total daily dose of the compound (I) is 50 to 100 ?g.Type: ApplicationFiled: February 10, 2012Publication date: June 7, 2012Applicant: GlaxoSmithKline Intellectual Property Management LimitedInventors: Keith Biggadike, Ian Buxton, Steven John Coote, Rosalyn Kay Nice, Kenton Lewis Reed, Amyn Sayani, Avinash Chander Sharma
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Publication number: 20100311706Abstract: There is provided a method of treatment of allergic rhinitis which comprises administering to a patient a pharmaceutically acceptable amount of a pharmaceutical formulation comprising an aqueous suspension of particulate compound of formula (I) or a solvate thereof, wherein the administration is once-per-day and intranasal, and the total daily dose of the compound (I) is 50 to 100 ?g.Type: ApplicationFiled: August 18, 2010Publication date: December 9, 2010Applicant: GLAXO GROUP LIMITEDInventors: Keith Biggadike, Ian Buxton, Steven John Coote, Rosalyn Kay Nice, Kenton Lewis Reed, Amyn Sayani, Avinash Chander Sharma
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Patent number: 6051224Abstract: Methods of modulating pulmonary surfactant secretion and treating conditions such as respiratory distress syndrome, are provided. Compositions for delivering imaging and therapeutic agents through use of the monoclonal antibodies A2C and A2R or fragments thereof are provided. Methods for delivering selected effector molecules such as imaging, modulating and therapeutic agents through use of these compositions are also provided.Type: GrantFiled: February 28, 1996Date of Patent: April 18, 2000Assignee: Thomas Jefferson UniversityInventors: David S. Strayer, Avinash Chander