Abstract: A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.

Abstract: Systems and methods for periodically determining a stack error using a direct memory access (DMA) call are provided. The method may include periodically determining whether a stack pointer is beyond a limit in a stack through a direct memory access (DMA) call. The method may additionally include identifying a stack error based on a determination that the stack pointer is beyond the limit in the stack. In the method, a periodicity of the determination of whether the stack pointer is beyond the limit in the stack through the DMA call may be based on a size of space between the stack pointer and the limit in the stack.

Abstract: Systems and methods for periodically determining a stack error using a direct memory access (DMA) call are provided. The method may include periodically determining whether a stack pointer is beyond a limit in a stack through a direct memory access (DMA) call. The method may additionally include identifying a stack error based on a determination that the stack pointer is beyond the limit in the stack. In the method, a periodicity of the determination of whether the stack pointer is beyond the limit in the stack through the DMA call may be based on a size of space between the stack pointer and the limit in the stack.

Abstract: A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.

Abstract: A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.

Abstract: A device having a co-operative scheduler of a task of an application, a timer circuit to detect a task of the application executing longer than an expected execution time for the task without interrupting execution of the task; and a record circuit to record that a task has been detected by the timer circuit executing longer than the expected execution time. A method for co-operative scheduling of tasks of an application, detecting a task of an application executing longer than an expected execution time for the task without interrupting execution of the task, and recording that an overrun has been detected.

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

Abstract: A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

Abstract: A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.