Patents by Inventor Avinash J V

Avinash J V has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Isolating a region of a system on a chip for safety critical operations
    Patent number: 11803668
    Abstract: In various examples, an integrated circuit includes first and second portions operating within separate domains. The second portion has an interface that connects the first and second portions. The second portion selectively locks the interface to prevent communication with the first portion over the interface, and selectively unlocks the interface to allow communication with the first portion over the interface.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: October 31, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Padam Patt Krishnani, Avinash J V, Anirban Ghosh, Phanikumar Parvatham, Vamshikrishna Yalamaddi, Srinivasa Reddy Kalluri
  • Transmitting data between regions of varying safety integrity levels in a system on a chip
    Patent number: 11573856
    Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Michael Ditty, Hari U. Krishnan, Padam Patt Krishnani, Jyotirmaya Swain, Anirban Ghosh, Shraddha Manohar Gondkar, Avinash J V, Phanikumar Parvatham
  • TRANSMITTING DATA BETWEEN REGIONS OF VARYING SAFETY INTEGRITY LEVELS IN A SYSTEM ON A CHIP
    Publication number: 20230036130
    Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.
    Type: Application
    Filed: September 16, 2021
    Publication date: February 2, 2023
    Inventors: Michael Ditty, Hari U. Krishnan, Padam Patt Krishnani, Jyotirmaya Swain, Anirban Ghosh, Shraddha Manohar Gondkar, Avinash J V, Phanikumar Parvatham
  • ISOLATING A REGION OF A SYSTEM ON A CHIP FOR SAFETY CRITICAL OPERATIONS
    Publication number: 20230036117
    Abstract: In various examples, an integrated circuit includes first and second portions operating within separate domains. The second portion has an interface that connects the first and second portions. The second portion selectively locks the interface to prevent communication with the first portion over the interface, and selectively unlocks the interface to allow communication with the first portion over the interface.
    Type: Application
    Filed: September 16, 2021
    Publication date: February 2, 2023
    Inventors: Padam Patt Krishnani, Avinash J V, Anirban Ghosh, Phanikumar Parvatham, Vamshikrishna Yalamaddi, Srinivasa Reddy Kalluri
  • COMMUNICATING FAULTS TO AN ISOLATED SAFETY REGION OF A SYSTEM ON A CHIP
    Publication number: 20230032305
    Abstract: In various examples, an integrated circuit includes first and second portions. The first portion includes a timer that starts when the first portion transmits at least one error signal to the second portion. The timer may reset when data corresponding to at least one fault has been cleared from the first portion. The first portion transmits a timeout error signal when the timer indicates at least a predetermined amount of time has elapsed. The second portion receives the at least one error signal and the timeout error signal when the timeout error signal has been sent. The second portion may notify an external system after the timeout error signal is received.
    Type: Application
    Filed: September 16, 2021
    Publication date: February 2, 2023
    Inventors: Padam Patt Krishnani, Avinash J V, Shraddha Manohar Gondkar, Sowmya Satya Venkata Naga Siva Sai Bindu Mandapati