Patents by Inventor Avinash Jindal

Avinash Jindal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Load balance connections per server in multi-core/multi-blade system
    Patent number: 9411656
    Abstract: A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 9, 2016
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Avinash Jindal, Deepak Bansal, Sam Htin Moy, David Cheung, Bing Wang, Mani Kancherla, Sridhar Devarapalli
  • Load Balance Connections Per Server In Multi-Core/Multi-Blade System
    Publication number: 20100325280
    Abstract: A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 23, 2010
    Applicant: Brocade Communications Systems, Inc.
    Inventors: Avinash Jindal, Deepak Bansal, Sam Htin Moy, David Cheung, Bing Wang, Mani Kancherla, Sridhar Devarapalli