Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

Abstract: Protection of authentication tag computation against power and electromagnetic side-channel attacks is described. An example of one or more storage mediums includes instructions for performing a process for calculation of an authentication tag for a data encryption operation, including generating one or more random values; receiving multiple data blocks for calculation, and performing calculation utilizing the received data blocks and the one or more random values to generate intermediate values; performing a data accumulation operation to accumulate random values in calculation of the data blocks; and calculating the authentication tag based at least in part on the generated intermediate values and the accumulated random values.

Abstract: In one example an apparatus comprises an input state register, and a first round secure hash algorithm (SHA) datapath circuit communicatively coupled to the input state register and a second round secure hash algorithm (SHA) datapath circuit communicatively coupled to the first round secure hash datapath circuit, the first round secure has algorithm (SHA) datapath circuit and the second round secure hash algorithm (SHA) datapath circuit each comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step calculation, a third section to perform a ? step of the SHA calculation, a fourth section to perform a ? step of the SHA calculation, and a fifth section to perform a ? step of the SHA calculation.

Abstract: A security processor includes a scheduler to read input data blocks from an input buffer, send the input data blocks to one or more cryptographic circuits in a first random order; and send data blocks having random values in a second random order to one or more of the cryptographic circuits that did not receive the input data blocks.

Abstract: Protection of authentication tag computation against power and electromagnetic side-channel attacks is described. An example of one or more storage mediums includes instructions for performing a process for calculation of an authentication tag for a data encryption operation, including generating one or more random values; receiving multiple data blocks for calculation, and performing calculation utilizing the received data blocks and the one or more random values to generate intermediate values; performing a data accumulation operation to accumulate random values in calculation of the data blocks; and calculating the authentication tag based at least in part on the generated intermediate values and the accumulated random values.

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.

Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform an incomplete number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format, the plurality of compute nodes comprising at least a first NTT circuit comprising a single butterfly circuit to perform a series of butterfly calculations on input data; and a randomizing circuitry to randomize an order of the series of butterfly calculations.

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

Abstract: An apparatus is described including cryptography circuitry to generate authentication tags to provide integrity protection for plaintext and ciphertext.

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

Abstract: Various systems and methods may benefit from determination of environmental signatures in recordings. For example, such signatures may aid forensic analysis and alignment of media recordings, such as alignment of audio or video recordings. A method can include reading data representative of sensed light in a visual track of a video recording. The method can also include extracting an electric network frequency signal from the data representative of sensed light.

Abstract: Various systems and methods may benefit from determination of environmental signatures in recordings. For example, such signatures may aid forensic analysis and alignment of media recordings, such as alignment of audio or video recordings. A method can include reading data representative of sensed light in a visual track of a video recording. The method can also include extracting an electric network frequency signal from the data representative of sensed light.

Abstract: A confidentiality preserving system and method for performing a rank-ordered search and retrieval of contents of a data collection. The system includes at least one computer system including a search and retrieval algorithm using term frequency and/or similar features for rank-ordering selective contents of the data collection, and enabling secure retrieval of the selective contents based on the rank-order. The search and retrieval algorithm includes a baseline algorithm, a partially server oriented algorithm, and/or a fully server oriented algorithm. The partially and/or fully server oriented algorithms use homomorphic and/or order preserving encryption for enabling search capability from a user other than an owner of the contents of the data collection. The confidentiality preserving method includes using term frequency for rank-ordering selective contents of the data collection, and retrieving the selective contents based on the rank-order.