Patents by Inventor Avinash Pandit

Avinash Pandit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250299128
    Abstract: Operation of various data servers included in a cloud data server are monitored and controlled to prevent a client from exceeding their available budget for hosting their workloads at the cloud server. Business rules and associated actions can be configured regarding operational cost/usage of hosting client workloads versus an available budget. As a cost approaches or exceeds a defined budget, respective operations and number of available data servers can be auto-scaled/throttled to prevent the client from exceeding the budget while attempting to maintain operation of as many workloads as possible. An operational budget, and also operational spend, throughout a given budget cycle can be predicted. A current cost/usage can be compared with the predicted budget/usage and a current operation of the cloud server can adjusted based on similarity/dissimilarity between the current cost/usage and the predicted budget/usage.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 25, 2025
    Inventors: Ophir Buchman, Junneng Nie, Jintai Han, Yuehua Liu, Kaixing Si, Susheelkumar Jain, Avinash Pandit
  • Publication number: 20230350453
    Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: SHIV HARIT MATHUR, Avinash Pandit
  • Patent number: 11803207
    Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 31, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shiv Harit Mathur, Avinash Pandit