Patents by Inventor Avinash PHILIP

Avinash PHILIP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power reduction via memory efficiency compensation
    Patent number: 10613612
    Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 7, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Sankaran Nampoothiri, Subodh Singh, Abhishek Ranka, Avinash Philip
  • Increasing caching efficiency using cache data patterns
    Patent number: 10489300
    Abstract: Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Sankaran Nampoothiri, Subodh Singh, ShankarGanesh Kandasamy, Avinash Philip
  • POWER REDUCTION VIA MEMORY EFFICIENCY COMPENSATION
    Publication number: 20180267595
    Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 20, 2018
    Inventors: Sankaran NAMPOOTHIRI, Subodh SINGH, Abhishek RANKA, Avinash PHILIP