Patents by Inventor Avinash Rath

Avinash Rath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941014
    Abstract: Methods, systems, and computer-readable media for versioned metadata management for a time-series database are disclosed. A metadata service of a distributed time-series database stores, to one or more metadata storage resources, first metadata descriptive of a table. The first metadata is associated with a version number in a logical sequence for the table. The metadata service stores, in a log, data indicative of one or more metadata updates for the table. The metadata update(s) are associated with an additional version number higher than the version number in the logical sequence. Responsive to a read request, the metadata service determines a most recent version number that has been applied from the log to the metadata storage resource(s). Responsive to the read request and based (at least in part) on the most recent version number, the metadata service returns either the first metadata or second metadata comprising the update(s).
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: March 26, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Sudipto Das, Kanishka Chaturvedi, Timothy A Rath, Avinash Goutham Reddy Aluguvelly
  • Patent number: 8813019
    Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 19, 2014
    Assignee: NVIDIA Corporation
    Inventors: Avinash Rath, Sanjith Sleeba, Ashish Kumar