Patents by Inventor Avinash Sodani
Avinash Sodani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966857Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation/function. The inline post processing unit is further configured to accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables, and stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.Type: GrantFiled: April 6, 2021Date of Patent: April 23, 2024Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ulf Hanebutte, Chia-Hsin Chen
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Patent number: 11934965Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation/function. The inline post processing unit is further configured to accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables, and stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.Type: GrantFiled: April 6, 2021Date of Patent: March 19, 2024Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ulf Hanebutte, Chia-Hsin Chen
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Patent number: 11934863Abstract: A system to support a machine learning (ML) operation comprises an array-based inference engine comprising a plurality of processing tiles each comprising at least one or more of an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform one or more computation tasks on the data in the OCM by executing a set of task instructions. The system also comprises a data streaming engine configured to stream data between a memory and the OCMs and an instruction streaming engine configured to distribute said set of task instructions to the corresponding processing tiles to control their operations and to synchronize said set of task instructions to be executed by each processing tile, respectively, to wait current certain task at each processing tile to finish before starting a new one.Type: GrantFiled: April 22, 2021Date of Patent: March 19, 2024Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Senad Durakovic, Gopal Nalamalapu
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Patent number: 11927932Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.Type: GrantFiled: March 20, 2023Date of Patent: March 12, 2024Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ramacharan Sundararaman, James Eldredge, Richard Taylor
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Patent number: 11868475Abstract: A new approach is proposed that contemplates systems and methods to support post reset fuse reload for latency reduction. First, values of fuses are read once and stored into one or more load registers on an electronic device, wherein the load registers are protected. Once the values of the fuse are loaded into the load registers, a valid indicator of the load registers is set indicating that the values have been successfully loaded into the load registers. When other components of the electronic device need to access these values, the other components will check the load registers first. If it is determined that the valid indicator of the load registers is set, the stored values are read from the load registers instead of from the fuses. If the valid indicator of the load registers is not set, the values are loaded again from the fuses into the load registers.Type: GrantFiled: October 31, 2020Date of Patent: January 9, 2024Assignee: Marvell Asia Pte LtdInventors: Ramacharan Sundararaman, Nithyananda Miyar, Martin Kovac, Avinash Sodani, Raghuveer Shivaraj
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Patent number: 11842197Abstract: A new approach for supporting tag-based synchronization among different tasks of a machine learning (ML) operation. When a first task tagged with a set tag indicating that one or more subsequent tasks need to be synchronized with it is received at an instruction streaming engine, the engine saves the set tag in a tag table and transmits instructions of the first task to a set of processing tiles for execution. When a second task having an instruction sync tag indicating that it needs to be synchronized with one or more prior tasks is received at the engine, the engine matches the instruction sync tag with the set tags in the tag table to identify prior tasks that the second task depends on. The engine holds instructions of the second task until these matching prior tasks have been completed and then releases the instructions to the processing tiles for execution.Type: GrantFiled: February 28, 2023Date of Patent: December 12, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Gopal Nalamalapu
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Patent number: 11829492Abstract: A new approach is proposed to support hardware-based protection for registers of an electronic device. Sources requesting access to the registers are categorized into a set of internal sources that can be trusted and a set of external sources that are untrusted. The registers are classified into a set of internal registers allowed to be accessed by the internal resources only, a set of read-only external registers that can be read by the external resources in addition to accessed by the internal resources, and a set of read/write external registers that can be read and written by both the internal and the external resources. Each access request by a source to the registers includes the source type, wherein access request is granted or denied based on the matching between the source bits in the access request and the register classification bits of the one or more registers to be accessed.Type: GrantFiled: January 29, 2021Date of Patent: November 28, 2023Assignee: Marvell Asia Pte LtdInventors: Ramacharan Sundararaman, Saurabh Shrivastava, Avinash Sodani, Nithyananda Miyar
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Patent number: 11789513Abstract: A system includes a multicore chip configured to perform machine learning (ML) operations. The system also includes a power monitoring module configured to measure power consumption of the multicore chip on a main power rail of the multicore chip. The power monitoring module is further configured to assert a signal in response to the measured power consumption exceeding a first threshold. The power monitoring module is further configured to transmit the asserted signal to a power throttling module to initiate a power throttling for the multicore chip.Type: GrantFiled: May 27, 2022Date of Patent: October 17, 2023Assignee: Marvell Asia Pte LtdInventors: Atul Bhattarai, Srinivas Sripada, Avinash Sodani, Michael Dudek, Darren Walworth, Roshan Fernando, James Irvine, Mani Gopal
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Patent number: 11734608Abstract: A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.Type: GrantFiled: December 23, 2020Date of Patent: August 22, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ramacharan Sundararaman
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Publication number: 20230229129Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Avinash Sodani, Ramacharan Sundararaman, James Eldredge, Richard Taylor
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Publication number: 20230205540Abstract: A new approach for supporting tag-based synchronization among different tasks of a machine learning (ML) operation. When a first task tagged with a set tag indicating that one or more subsequent tasks need to be synchronized with it is received at an instruction streaming engine, the engine saves the set tag in a tag table and transmits instructions of the first task to a set of processing tiles for execution. When a second task having an instruction sync tag indicating that it needs to be synchronized with one or more prior tasks is received at the engine, the engine matches the instruction sync tag with the set tags in the tag table to identify prior tasks that the second task depends on. The engine holds instructions of the second task until these matching prior tasks have been completed and then releases the instructions to the processing tiles for execution.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Inventors: Avinash Sodani, Gopal Nalamalapu
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Patent number: 11687837Abstract: A system to support a machine learning (ML) operation comprises a core configured to receive and interpret commands into a set of instructions for the ML operation and a memory unit configured to maintain data for the ML operation. The system further comprises an inference engine having a plurality of processing tiles, each comprising an on-chip memory (OCM) configured to maintain data for local access by components in the processing tile and one or more processing units configured to perform tasks of the ML operation on the data in the OCM. The system also comprises an instruction streaming engine configured to distribute the instructions to the processing tiles to control their operations and to synchronize data communication between the core and the inference engine so that data transmitted between them correctly reaches the corresponding processing tiles while ensuring coherence of data shared and distributed among the core and the OCMs.Type: GrantFiled: June 27, 2022Date of Patent: June 27, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Gopal Nalamalapu
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Patent number: 11687136Abstract: A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.Type: GrantFiled: April 22, 2022Date of Patent: June 27, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen, Nikhil Jayakumar
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Patent number: 11635739Abstract: A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.Type: GrantFiled: April 30, 2020Date of Patent: April 25, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ramacharan Sundararaman, James Eldredge, Richard Taylor
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Patent number: 11621923Abstract: Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.Type: GrantFiled: December 22, 2020Date of Patent: April 4, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Enric Musoll, Dan Tu, Chia-Hsin Chen
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Publication number: 20230096994Abstract: A method of converting a data stored in a memory from a first format to a second format is disclosed. The method includes extending a number of bits in the data stored in a double data rate (DDR) memory by one bit to form an extended data. The method further includes determining whether the data stored in the DDR is signed or unsigned data. Moreover, responsive to determining that the data is signed, a sign value is added to the most significant bit of the extended data and the data is copied to lower order bits of the extended data. Responsive to determining that the data is unsigned, the data is copied to lower order bits of the extended data and the most significant bit is set to an unsigned value, e.g., zero. The extended data is stored in an on-chip memory (OCM) of a processing tile of a machine learning computer array.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Inventors: Avinash Sodani, Ulf Hanebutte, Chia-Hsin Chen
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Patent number: 11604683Abstract: A new approach for supporting tag-based synchronization among different tasks of a machine learning (ML) operation. When a first task tagged with a set tag indicating that one or more subsequent tasks need to be synchronized with it is received at an instruction streaming engine, the engine saves the set tag in a tag table and transmits instructions of the first task to a set of processing tiles for execution. When a second task having an instruction sync tag indicating that it needs to be synchronized with one or more prior tasks is received at the engine, the engine matches the instruction sync tag with the set tags in the tag table to identify prior tasks that the second task depends on. The engine holds instructions of the second task until these matching prior tasks have been completed and then releases the instructions to the processing tiles for execution.Type: GrantFiled: April 30, 2020Date of Patent: March 14, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Gopal Nalamalapu
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Patent number: 11551148Abstract: A method of converting a data stored in a memory from a first format to a second format is disclosed. The method includes extending a number of bits in the data stored in a double data rate (DDR) memory by one bit to form an extended data. The method further includes determining whether the data stored in the DDR is signed or unsigned data. Moreover, responsive to determining that the data is signed, a sign value is added to the most significant bit of the extended data and the data is copied to lower order bits of the extended data. Responsive to determining that the data is unsigned, the data is copied to lower order bits of the extended data and the most significant bit is set to an unsigned value, e.g., zero. The extended data is stored in an on-chip memory (OCM) of a processing tile of a machine learning computer array.Type: GrantFiled: April 29, 2020Date of Patent: January 10, 2023Assignee: Marvell Asia Pte LtdInventors: Avinash Sodani, Ulf Hanebutte, Chia-Hsin Chen
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Publication number: 20220405937Abstract: A new approach is proposed to support real-time camera-based agriculture inspection. One or more cameras are associated with a vehicle moving through a farm, wherein the one or more cameras each captures a plurality of images and/or video streams for an up-close, under-the-canopy view of crops on the farm. A compute box onboard the vehicle retrieves and processes the captured images and/or video streams to extract insights about current status of the crops on the farm and transmit the insights to a monitoring app running on a mobile computing device to be viewed as an inspection record by a user, e.g., farmer in real time as soon as the images and/or the video streams have been processed. The user may then control the compute box and/or the one or more cameras via the monitoring app accordingly while the vehicle is moving through the farm.Type: ApplicationFiled: June 9, 2022Publication date: December 22, 2022Inventor: Avinash Sodani
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Patent number: 11526440Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.Type: GrantFiled: June 6, 2019Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Avinash Sodani, Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo