Abstract: Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store.

Abstract: A method and apparatus for enabling an adaptive replay loop in a processor. More particularly, the present invention relates to allowing instructions in the replay loop to change its relative position, thereby decreasing the latency for execution of instructions, resolving dynamic resource conflicts, and also increasing the overall efficiency of the processor.

Abstract: Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.

Abstract: Embodiments of the present invention relate to selectively re-executing instructions in a computer processor based on their association with a particular cache miss.

Abstract: Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements.

Abstract: Embodiments of the present invention relate to a system and method for associating a register file cache with a register file in a computer processor.

Abstract: A method and apparatus for a microprocessor with a divided register alias table is disclosed. In one embodiment, a first register alias table may have a full set of read and write ports, and a second register alias table may have a smaller set of read and write ports. The second register alias table may include translations for those logical register addresses that are used less frequently. When the second register alias table is called upon to translate more logical register addresses than it has read ports, in one embodiment a pipeline stall may permit additional time to utilize the limited read ports. In another embodiment, additional build rules for a trace cache may be utilized.

Abstract: According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.

Abstract: A method and system for multiple branch paths in a microprocessor is described. The method includes assigning an identification number (ID) to each of a plurality of micro-operations (uops) to identify a branch path to which the uop belongs, determining whether one or more branches are predicted correctly, determining which of the one or more branch paths are dependent on a mispredicted branch, and determining whether one or more of the plurality of uops belong to a branch path that is dependent on a mispredicted branch based on their assigned IDs.

Abstract: A computer architecture allowing reuse of previously determined instruction results, indexes instruction results according to instruction addresses. The continued validity of operand values in registers or memory for the instructions is determined prior to the fetching of any given instruction by an invalidation system which detects an intervening register or memory write. Thus, the need to evaluate the operand values themselves which would delay execution is avoided. In one embodiment, dependencies for operands between instructions are recorded so as to avoid invalidating instructions having operand register or memory locations which are overwritten when the overwriting will be corrected by an intervening instruction immediately preceding the dependent instructions.