Patents by Inventor Avinash Somalinga Suresh

Avinash Somalinga Suresh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11270051
    Abstract: Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data flow graph into a plurality of sub-graphs based on the classifying, wherein each sub-graph corresponds to a different one of the plurality of systems. From each sub-graph, a portion of high-level language (HLL) program code can be generated. Each portion of HLL program code may be specific to the system corresponding to the sub-graph from which the portion of HLL program code was generated.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 8, 2022
    Assignee: Xilinx, Inc.
    Inventors: Avinash Somalinga Suresh, Ali Behboodian
  • Patent number: 10846449
    Abstract: A design tool executing on a computer system converts a block model of a circuit design to a high-level language (HLL) specification. The design tool then converts the HLL specification to a hardware description language (HDL) specification. Circuit implementation data is generated from the HDL specification by the design tool, and the circuit implementation data can be used to make an integrated circuit that performs functions specified by the circuit design.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 24, 2020
    Assignee: Xilinx, Inc.
    Inventors: Avinash Somalinga Suresh, Nabeel Shirazi, Daniel E. Michek, Daniel G. Gibbons
  • Patent number: 10740529
    Abstract: Circuit designs and/or circuitry for integrated circuits (ICs) can be generated for radio-frequency (RF) applications by determining, using computer hardware, a value of a parameter of a super-sampling rate (SSR) block within a model of a circuit, wherein the value indicates a number of a plurality of data channels of the SSR block, automatically creating, using the computer hardware, a primary input port and a primary output port for the SSR block based on functionality of the SSR block, wherein vector size of the primary input port and the primary output port is determined from the value of the parameter, automatically creating, using the computer hardware, a plurality of scalar instances of the SSR block based on the value of the parameter, wherein the plurality of scalar instances are arranged in parallel, and configuring, using the computer hardware, each scalar instance of the plurality of scalar instances based on a parameterization of the SSR block.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 11, 2020
    Assignee: Xilinx, Inc.
    Inventors: Avinash Somalinga Suresh, Narendra Kumar Anumolu
  • Patent number: 10706193
    Abstract: Approaches for simulating and processing a circuit design involve recognizing by a design processing tool a replaceable subsystem in a circuit design having multiple blocks. The replaceable subsystem includes a subset of the blocks. The design tool converts the subset of blocks into an executable program and schedules activation of blocks of the circuit design other than the subset of blocks during simulation of the circuit design. The scheduled blocks are activated during simulation according to the scheduling, and activation of the subset of the plurality of blocks is bypassed during simulation with a call to the executable program.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 7, 2020
    Assignee: Xilinx, Inc.
    Inventors: David Van Campenhout, Avinash Somalinga Suresh, Ali Behboodian
  • Patent number: 10586003
    Abstract: Using high level synthesis (HLS) and linked hardware description language (HDL) libraries to implement a circuit design includes generating, using computer hardware, a data flow graph from a model that includes an HDL model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code, and dividing, using the computer hardware, the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block. Using the computer hardware, a first HDL core is generated from the first sub-graph, synthesizable program code is generated form the second sub-graph, HLS is performed on the synthesizable program code to generate a second HDL core, and the circuit design is generated including the first HDL core connected to the second HDL core.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 10, 2020
    Assignee: XILINX, INC.
    Inventor: Avinash Somalinga Suresh