Patents by Inventor . Avinash

. Avinash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10127659
    Abstract: Methods and apparatus for improved deep learning for image acquisition are provided. An imaging system configuration apparatus includes a training learning device including a first processor to implement a first deep learning network (DLN) to learn a first set of imaging system configuration parameters based on a first set of inputs from a plurality of prior image acquisitions to configure at least one imaging system for image acquisition, the training learning device to receive and process feedback including operational data from the plurality of image acquisitions by the at least one imaging system. The example apparatus includes a deployed learning device including a second processor to implement a second DLN, the second DLN generated from the first DLN of the training learning device, the deployed learning device configured to provide a second imaging system configuration parameter to the imaging system in response to receiving a second input for image acquisition.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: November 13, 2018
    Assignee: General Electric Company
    Inventors: Jiang Hsieh, Gopal Avinash, Saad Sirohey
  • Patent number: 10121129
    Abstract: The ELECTRONIC WALLET CHECKOUT PLATFORM APPARATUSES, METHODS AND SYSTEMS (“EWCP”) transform customer purchase requests triggering electronic wallet applications via EWCP components into electronic purchase confirmation and receipts. In one implementation, the EWCP receives a merchant payment request, and determines a payment protocol handler associated with the merchant payment request. The EWCP instantiates a wallet application via the payment protocol handler. The EWCP obtains a payment method selection via the wallet application, wherein the selected payment method is one of a credit card, a debit card, a gift card selected from an electronic wallet, and sends a transaction execution request for a transaction associated with the merchant payment request. Also, the EWCP receives a purchase response to the transaction execution request, and outputs purchase response information derived from the received purchase response.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: November 6, 2018
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventor: Avinash Kalgi
  • Publication number: 20180312740
    Abstract: A wellbore fluid treatment may include a compound formed from reaction between cyclic anyhydride pendant groups on a polymer backbone with at least one amino acid, neutralized with a nitrogen containing compound. Methods may include injecting such a compound into a hydrogen production stream. Other methods may include reacting polybutadiene grafted maleic anhydride with at least one amino acid to produce an intermediate; and reacting the intermediate with an amide, amine, or imidazoline having at least a C4-C24 group to produce a compound.
    Type: Application
    Filed: June 8, 2016
    Publication date: November 1, 2018
    Applicants: M-I L.L.C., M-I L.L.C.
    Inventors: Avinash Pradyumna Deshpande, Yeshwant Shekhar Khandekar
  • Patent number: 10114903
    Abstract: When requested content is available at a data center, the data center returns the requested content to the data center. When the requested content is locally unavailable at the data center, the requested content is retrieved from an origin server. The retrieval of the content from the origin server may be delayed based on the processing load at the origin server. When retrieval of the content is delayed, the request is prioritized and placed in a queue for handling by the origin server based on the priority of the request. Also, when retrieval of the content is delayed, a status page may be communicated to the browser to inform a user of the delay and provide alternate content and status information related to the request determined as a function of the request or the current state of the origin server.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: October 30, 2018
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, David K. Davidson, Avinash C. Saxena
  • Publication number: 20180303800
    Abstract: The present disclosure provides substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes, of Formula I D-M-D??(Formula I) useful as antiviral agents. In certain embodiments disclosed herein M is a group —P-A-P— where A is Certain substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes disclosed herein are potent and/or selective inhibitors of viral replication, particularly Hepatitis C virus replication. Pharmaceutical compositions/and combinations containing one or more substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes and a pharmaceutically acceptable carrier are also provided by this disclosure. Methods for treating viral infections, including Hepatitis C viral infections are provided by the disclosure.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Jason Allan Wiles, Qiuping Wang, Akihiro Hashimoto, Godwin Pais, Xiangzhu Wang, Venkat Gadhachanda, Avinash Phadke, Milind Deshpande, Dawei Chen
  • Publication number: 20180309594
    Abstract: In an integrated Layer 2-layer 3 hybrid VPN network a Layer 3 provider edge device that runs in an EVPN domain and a Layer 3 VPN domain defines an interconnect point between the EVPN domain and the Layer 3 VPN domain. The Layer 3 provider edge device receives an IP prefix for a Layer 3 customer edge device disposed in the Layer 3 VPN domain. The Layer 3 provider edge device receives a MAC address, an IP address and a next hop address for an EVPN customer edge device disposed in the EVPN domain from an EVPN provider edge device disposed in the EVPN domain. The Layer 3 provider edge device leaks the IP prefix to the EVPN domain and transmits state information to the EVPN customer edge device.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Inventors: James Uttaro, Avinash Lingala
  • Publication number: 20180305375
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement Factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof wherein R12 or R13 on the A group is an aryl, heteroaryl or heterocycle (R32) are provided. The inhibitors of Factor D described herein reduce the excessive activation of complement.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 25, 2018
    Applicant: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Avinash S. Phadke, Milind Deshpande, Atul Agarwal, Dawei Chen, Venkat Rao Gadhachanda, Akihiro Hashimoto, Godwin Pais, Qiuping Wang, Xiangzhu Wang
  • Publication number: 20180303090
    Abstract: Treatment compositions which may be use to impart an antimicrobial benefit to animate and inanimate surfaces, e.g, topical compositions and hard surface and soft surface treatment compositions comprising specific surfactant comprising anionic surfactants, or anionic and nonionic surfactant systems.
    Type: Application
    Filed: October 17, 2016
    Publication date: October 25, 2018
    Inventors: Avinash BUDHIAN, Sarah Frances DE SZALAY, Richard GILES, Aleksandra KRUSZEWSKA, Pamela MCGOWAN
  • Patent number: 10108526
    Abstract: A method of searching a corpus including a plurality of files includes automatically determining, using a processor, a historical ranking for each file using respective changeset information. Search term(s) of a query are received. A textual ranking is determined for each file using the search term(s) and contents of that file. The historical and textual rankings are combined to provide a result ranking. A data processing system includes a storage system storing the corpus including the plurality of files, a processor configured to determine the result rankings, and a user interface system configured to receive query results from the processor and present them to a user.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: October 23, 2018
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Bunyamin Sisman, Avinash C. Kak
  • Patent number: 10106563
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof wherein R12 or R13 on the A group is an ether (R32) are provided. The inhibitors described herein target factor D and inhibit or regulate the complement cascade at an early and essential point in the alternative complement pathway, and reduce factor D's ability to modulate the classical and lectin complement pathways. The inhibitors of factor D described herein are capable of reducing the excessive activation of complement, which has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 23, 2018
    Assignee: Achillion Pharmaecuticals, Inc.
    Inventors: Jason Allan Wiles, Venkat Rao Gadhachanda, Godwin Pais, Akihiro Hashimoto, Qiuping Wang, Dawei Chen, Xiangzhu Wang, Atul Agarwal, Milind Deshpande, Avinash S. Phadke
  • Publication number: 20180298043
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof, wherein R12 or R13 on the A group is an alkyne (R32) are provided. The inhibitors described herein target factor D and inhibit or regulate the complement cascade at an early and essential point in the alternative complement pathway, and reduce factor D's ability to modulate the classical and lectin complement pathways. The inhibitors of factor D described herein are capable of reducing the excessive activation of complement, which has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 18, 2018
    Applicant: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Godwin Pais, Akihiro Hashimoto, Venkat Rao Gadhachanda, Qiuping Wang, Dawei Chen, Xiangzhu Wang, Atul Agarwal, Milind Deshpande, Avinash S. Phadke
  • Publication number: 20180302101
    Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 18, 2018
    Inventors: Avinash Gutta, Venkata Aruna Srikanth Nittala, Abhilasha Kawle
  • Patent number: 10103744
    Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 16, 2018
    Assignee: Analog Devices Global
    Inventors: Avinash Gutta, Venkata Aruna Srikanth Nittala, Abhilasha Kawle
  • Patent number: 10103540
    Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 16, 2018
    Assignee: General Electric Company
    Inventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Joe Walter Kirstein, Alexander Viktorovich Bolotnikov
  • Patent number: 10102129
    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Krishna N. Vinod, Avinash Sodani, Zainulabedin J. Aurangabadwala
  • Patent number: 10100072
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof wherein R12 or R13 on the A group is a phosphonate (R32) are provided. The inhibitors described herein target factor D and inhibit or regulate the complement cascade at an early and essential point in the alternative complement pathway, and reduce factor D's ability to modulate the classical and lectin complement pathways. The inhibitors of factor D described herein are capable of reducing the excessive activation of complement, which has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 16, 2018
    Assignee: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Akihiro Hashimoto, Venkat Rao Gadhachanda, Godwin Pais, Qiuping Wang, Dawei Chen, Xiangzhu Wang, Atul Agarwal, Milind Deshpande, Avinash Phadke
  • Publication number: 20180291046
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof, wherein R12 or R13 on the A group is an alkyne (R32) are provided. The inhibitors described herein target factor D and inhibit or regulate the complement cascade at an early and essential point in the alternative complement pathway, and reduce factor D's ability to modulate the classical and lectin complement pathways. The inhibitors of factor D described herein are capable of reducing the excessive activation of complement, which has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Applicant: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Godwin Pais, Akihiro Hashimoto, Venkat Rao Gadhachanda, Qiuping Wang, Dawei Chen, Xiangzhu Wang, Atul Agarwal, Milind Deshpande, Avinash S. Phadke
  • Publication number: 20180291047
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof, wherein R12 or R13 on the A group is an alkyne (R32) are provided. The inhibitors described herein target factor D and inhibit or regulate the complement cascade at an early and essential point in the alternative complement pathway, and reduce factor D's ability to modulate the classical and lectin complement pathways. The inhibitors of factor D described herein are capable of reducing the excessive activation of complement, which has been linked to certain autoimmune, inflammatory, and neurodegenerative diseases, as well as ischemia-reperfusion injury and cancer.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Applicant: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Godwin Pais, Akihiro Hashimoto, Venkat Rao Gadhachanda, Qiuping Wang, Dawei Chen, Xiangzhu Wang, Atul Agarwal, Milind Deshpande, Avinash S. Phadke
  • Patent number: 10092547
    Abstract: The present disclosure provides substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes, of Formula I D-M-D??(Formula I) useful as antiviral agents. In certain embodiments disclosed herein M is a group —P-A-P— where A is Certain substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes disclosed herein are potent and/or selective inhibitors of viral replication, particularly Hepatitis C virus replication. Pharmaceutical compositions/and combinations containing one or more substituted aliphanes, cyclophanes, heteraphanes, heterophanes, hetero-heteraphanes and metallocenes and a pharmaceutically acceptable carrier are also provided by this disclosure. Methods for treating viral infections, including Hepatitis C viral infections are provided by the disclosure.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 9, 2018
    Assignee: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Qiuping Wang, Akihiro Hashimoto, Godwin Pais, Xiangzhu Wang, Venkat Gadhachanda, Avinash Phadke, Milind Deshpande, Dawei Chen
  • Patent number: 10092584
    Abstract: Compounds, methods of use, and processes for making inhibitors of complement Factor D comprising Formula I, or a pharmaceutically acceptable salt or composition thereof. The inhibitors described herein target Factor D and inhibit or regulate the complement cascade. The inhibitors of Factor D described herein reduce the excessive activation of complement.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 9, 2018
    Assignee: Achillion Pharmaceuticals, Inc.
    Inventors: Jason Allan Wiles, Avinash S. Phadke, Milind Deshpande, Atul Agarwal, Dawei Chen, Venkat Rao Gadhachanda, Akihiro Hashimoto, Godwin Pais, Qiuping Wang, Xiangzhu Wang