Patents by Inventor Avinoam Kolodny
Avinoam Kolodny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200192675Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: ApplicationFiled: November 29, 2019Publication date: June 18, 2020Inventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Patent number: 10521237Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: GrantFiled: March 19, 2014Date of Patent: December 31, 2019Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTDInventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Patent number: 9754203Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables.Type: GrantFiled: March 19, 2014Date of Patent: September 5, 2017Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD.Inventors: Dotan Di Castro, Daniel Soudry, Shahar Kvatinsky, Asaf Gal, Avinoam Kolodny
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Patent number: 9659650Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.Type: GrantFiled: February 17, 2015Date of Patent: May 23, 2017Assignee: TECHNION RESEARCH & DEVELOPEMENT FOUNDATION LTD.Inventors: Avinoam Kolodny, Shahar Kvatinsky, Ravi Patel, Eby Friedman
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Publication number: 20170019108Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.Type: ApplicationFiled: July 14, 2015Publication date: January 19, 2017Inventors: Shahar Kvatinsky, Avinoam Kolodny, Yifat Hanein
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Patent number: 9548741Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.Type: GrantFiled: July 14, 2015Date of Patent: January 17, 2017Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD.Inventors: Shahar Kvatinsky, Avinoam Kolodny, Yifat Hanein
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Publication number: 20170011797Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.Type: ApplicationFiled: February 17, 2015Publication date: January 12, 2017Inventors: Avinoam Kolodny, Shahar Kvatinsky, Ravi Patel, Eby Friedman
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Publication number: 20140325192Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: ApplicationFiled: March 19, 2014Publication date: October 30, 2014Applicant: Technion Research and Development Foundation LTD.Inventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Publication number: 20140289179Abstract: A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables;Type: ApplicationFiled: March 19, 2014Publication date: September 25, 2014Applicant: Technion Research and Development Foundation LTD.Inventors: Dotan Di Castro, Daniel Soudry, Shahar Kvatinsky, Asaf Gal, Avinoam Kolodny
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Patent number: 8225265Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.Type: GrantFiled: December 1, 2008Date of Patent: July 17, 2012Assignee: Technion Research & Development Foundation Ltd.Inventors: Arkadiy Morgenshtein, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
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Publication number: 20110022754Abstract: A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.Type: ApplicationFiled: December 7, 2008Publication date: January 27, 2011Applicant: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTDInventors: Israel Cidon, Avinoam Kolodny, Walter Zigmond Isask'har
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Publication number: 20090150847Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.Type: ApplicationFiled: December 1, 2008Publication date: June 11, 2009Applicant: Technion Research & Development Foundation Ltd.Inventors: Arkadiy Morgenshtein, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
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Publication number: 20020073389Abstract: A method system and apparatus for implementing clock delay insertion for modules of chips using programmable clock delay units are described. The system for adding a clock delay to the clock input of a module includes a module and a programmable clock delay unit pre-pended to the module and configured to add a programmed clock delay.Type: ApplicationFiled: December 13, 2000Publication date: June 13, 2002Inventors: Yaron Elboim, Avinoam Kolodny, Ran Ginosar
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Patent number: 4785199Abstract: Programmable logic gate structures employ pairs of complementary transistors. Programming of the transistors is accomplished either by voltage biasing a shared floating gate of a CMOS transistor pair or by providing a variable resistance serially or in parallel with each transistor. The variable resistance can be a fusible link or a semiconductor device having an alterable crystalline structure.Type: GrantFiled: September 22, 1986Date of Patent: November 15, 1988Assignee: Stanford UniversityInventors: Avinoam Kolodny, Yigal Brandman